Hi, Please help me in selection of ARM controller which supports the 9 bit multi processor communication in UART. My first choice is NXP LPC series. AT91SAM series also works.
Thanks.
Reason: 1. I want controller which is supported by keil compiler! 2. USB and Ethernet 3. 4 UART with one modem port. 4. Internal flash and RAM 5. Good support (forums,downloads,free TCP stack,example code etc)
Some of my friends also used other LPC series, they told me, there is good support from NXP.
IF they've used them, they must have the Datasheets - so ask them to check if there is 9-bit support.
Or, you can easiy download the Datasheets and check for yourself!
To narrow-down your choice, start here: http://www.keil.com/dd/search_parm.asp
I have gone through the reference manual of STM32F107xx and found that there is only 1.25K bytes dedicated RAM for USB and 4K bytes for Ethernet. Is it sufficient ????
Is ST providing a free TCP/IP stack for ethernet and free driver code for USB.
NXP LPC2368/LPC2378 do NOT support 9 Bit.
NXP LPC29xx supports 2 UART for RS485 (9 Bit). www.standardics.nxp.com/.../
Thanks John, You are right, LPC29xx series supports 9 bit mode.But do not contain ethernet (pls go through my requirment). LPC175x series also supports 9 bit mode but why it is described with RS485. I have decided to use a parity bit as a 9th bit for multiprocessor communication. when i transmit the address i will set parity to "1" and in data it is "0".
www.st.com/.../forums-cat-8900-23.html ?
-> use a parity bit as a 9th bit -<
You may need to turn off the UART FIFO.
-> use a parity bit as a 9th bit -< You may need to turn off the UART FIFO.
Why to turn off FIFO ?? Is receive buffer contains the data even if parity error occurs ?
To avoid that, wrong bytes get the wrong stick parity.
Is receive buffer contains the data even if parity error occurs ?
I don't know; because eventually, I didn't choose such a solution, so I didn't study it.
Description in UART receive buffer for LPC2478. Since PE (parity error), FE (framing error) and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U0LSR register, and then to read a byte from the UnRBR (receive buffer).
I think that mean "UART receive buffer contains data even if parity error (FE or BI) occurs, but to avoid wrong data read first check the error."
probably; but can you trust it?