SPI interrupt at wrong address

Is there any setting I should change to make compiler do that? There are only 8 bytes from one interrupt vector address to next. And with all the push/pop, I do need a LJUMP. At address 0023, compiler does have a LJMP for my UART interrupt, but I just don't know why it would not do it for SPI interrupt.

For the UART interrupt I have

static void com_isr (void) interrupt 4 using 2

Does a different bank help?

Is there any setting I should change to make compiler do that? There are only 8 bytes from one interrupt vector address to next. And with all the push/pop, I do need a LJUMP. At address 0023, compiler does have a LJMP for my UART interrupt, but I just don't know why it would not do it for SPI interrupt.

For the UART interrupt I have

static void com_isr (void) interrupt 4 using 2

Does a different bank help?

I do need a LJUMP. At address 0023, compiler does have a LJMP for my UART interrupt, but I just don't know why it would not do it for SPI interrupt.

Why don't you disassemble the instruction that is at address 0x53 and see what it is? I'll bet i can guess.

CODE    0053H     0003H     ABSOLUTE

And with all the push/pop, I do need a LJUMP.

And you got one. It's just not where you're looking for it. The LJMP is at 0x53, just where the interrupt vector for interrupt number 10 belongs. But it would be rather wasteful if the linker were to put nothing at all in the entire address range from 0x26 to 0x53. So it found something that fits in the gap and put it there. Your SPI interrupt routine apparently fit the bill.

If you wished, You could prevent that by ensuring that you do provide an ISR for all possible interrupts; eg,

static void dummyISRxx(void) interrupt xx
{
  for(;;);
}

You could use this to prevent any unexpected behaviour if one of the "unused" interrupts should, somehow, accidentally get enabled...

You guys are right. I do have a LJMP at 0x53.
Then I still do not know what causes my problem. In my interrupt routine, I basically toggle P4_0, but on my scope, I can see the P4_0 toggles even when chip select is high. Too bad that I can not post screen shot here, but basically my MOSI rest at 2.7V, and every 12.5 usec, there are two small pulses pull the voltage to 3.6V. P4_0 toggles at the rising edge of the first small pulse, and my chip select is solid high. I know the voltage is a little strange and I don't know what cause these small pulses, but if the chip select is high, then it should not trigger interrupt at all, right?
Any suggestions?
Thanks,

Can you post it somewhere else, and then provide a Link here?

Take me a while to bypass company firewall, but here you are:

www.flickr.com/.../42986638@N02/3963290758/

www.flickr.com/.../42986638@N02/3963290852/