Hi, I am trying SPI communication between two C8051F120. Master and slave in 3 wire mode config. first time master sends data correctly but second time it get shifted by 1 bit. Please help me for same.
You don't use slave select?
If the two processors boots at different times, then the master can produce a spurious clock toggle that the slave sees.
If the master starts to transmit before the slave is initialized, they will get out of sync.
If there is a noise glitch on the SPI clock signal, they will get out of sync.
Please explain exactly how you plan to get your slave to run synchronously with the master if (when) they get out of sync. The slave select signal is a very important signal, and expected to be used even if you only have one slave.
Without a slave select, you must implement self-clocking data, which means that you can't use all 8 bits for a normal transfer. You may have to teach the slave that any combination of 8 ones followed by 8 zero (in any shifted combination) represents the start of a transfer (to teach the slave the current shifted state) and then you have to shift your data correspondingly. And you would need to send an extra dummy byte at the end of the transfer, to make sure that you shift out any remaining data bits from the slave receive register.
Sounds simple? Maybe time to start thinking again about that slave select signal...