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another newbie question.
I have a piece of code that I am porting from PICC. In PICC, you can make reference to specific pins ("#define sclk GPIO5" for example), and in your code, you can write to sclk to change the pin output on GPOI5. This makes porting code or changing pin layout so much easier as you can simple redefine sclk to a different pin to make the code work.
ARM seems to prefer to change its pin output through IOSET / IOCLR.
To make the existing PICC code work, I would prefer to be able to define certain pins logically, and change their states by referencing their logic names.
how do you do that in ARM? Thanks in advance.
Yes, this is a common problem.
Some processors can completely remove the read+modify by having the operation performed all the way down at the specific memory cell - in this case GPIO - where there isn't a normal RAM address, but a combination of SET/CLEAR/DATA latches for each bit. This is very expensive, so it can't be expanded to a general range of memory, but works wonders for GPIO.
The 8051 on the other hand has settled for a very narrow range of bytes that can also be bit-addressd. The disadvantage here - besides the limited range - is that there is no indirect or indexed bit addressing.
The bit banding of the Cortex-M3 is a generalization with a 1MB address range spanned by a 32MB alias range, so the Cortex-M3 can't do it with just a write but have to suffer a more general read/modify/write, even if the read+modify is outside the core and not visible in the code.
The important thing is however where the read+modify happens. Using a PIN register with an ARM, it will happen inside the execution unit, so the core will always have to wait for the read before being able to do the modify. When done in the memory controller, it can be masked, allowing the core to continue full-speed, as long as the write buffer FIFO doesn't get full. But the read operation will slow down the emptying of the FIFO, increasing the probability of a write stall. And a processor without a write buffer FIFO will suffer on next access. If happening all the way at the memory cell, it will be identical to a normal write - the dedicated hardware will perform the OR or AND operation on-the-fly. This is the reason why a lot of manufacturers have added SET and CLEAR registers for the GPIO.