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Bug in Keil debugger?

Hi guys. I'm trying to simulate a code for MSC1210 (Texas Instruments). The problem is that I have serious doubts about the results of the simulation since I've detected the following situation:

I make an external memory access, which, as you all know, uses the Port 0 as both Address and data bus (the address will be latched to preserve its value for the address lines of the memory). The fact is that it succeeds, in spite of I forced several Port0 pins to LOW, simulating that there is a ground connected to them.

The simulation of this "forcing" is done by cliking the corresponding checkbox of that pins in the "Port0" simulated peripheral window.

I hope you help me. If you need any clarifying note tell me.

Thanks, and excuse my wrong english.

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  • ... has always been fraught with problems.

    one day you make a change and the bits on P0 from a movx match something the LCD 'understands" an KABOOM.

    Then you make some LCD access in main and some external memory access in an ISR and the LCD is enabled to 'see' the memory access bits.

    Just make it memory mapped I/O

    Signals and timing of LCD are quite different, so that the instruction MOVX is not going to work well unless I think of anything to solve this tradeoff.
    that is ludicrous, unless you have an extermely fast RAM or an extremely slow LCD, as you - in any sensible design - do not access external RAM for anything critical, you may have to slow RAM access down just a tad without any serious problems.

    If that is not possible add a couple of latches.

    Erik

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  • ... has always been fraught with problems.

    one day you make a change and the bits on P0 from a movx match something the LCD 'understands" an KABOOM.

    Then you make some LCD access in main and some external memory access in an ISR and the LCD is enabled to 'see' the memory access bits.

    Just make it memory mapped I/O

    Signals and timing of LCD are quite different, so that the instruction MOVX is not going to work well unless I think of anything to solve this tradeoff.
    that is ludicrous, unless you have an extermely fast RAM or an extremely slow LCD, as you - in any sensible design - do not access external RAM for anything critical, you may have to slow RAM access down just a tad without any serious problems.

    If that is not possible add a couple of latches.

    Erik

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