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ARM How to handle nested interrupts in LPC2300

shyam ST

Dear all
I am using Timer0 and external interrupt 0.
Timer0 of having 10ms.
External interrupt ISR required 50ms to compltet its task, so that I am not getting exactly 10ms interrupt of Timer0.

I also use IENABLE and IDISABLE as told in sample code examples.but still i am not getting result.
I am working on LPC2378 and using
"REAL VIEW MDK-ARM Ver 3.20"

Regards
SS T.
Pune India

Parents
  • 0 in reply to Catcus Blip

    Here is Ext0 ISR

    void EXT0_ISR (void) __irq
    { EXTINT = 0x01;

    IENABLE; TransmitChar0('E');

    Timer1Delay(50); // delay for 50ms sec

    TransmitChar0('I'); TransmitChar0('N'); TransmitChar0('T');

    IDISABLE; VICVectAddr = 0;
    }

    And Timer0 is 10ms.
    After putting IENABLE & IDISABLE.
    processor stop working.

    regards
    SS T.

Reply
  • 0 in reply to Catcus Blip

    Here is Ext0 ISR

    void EXT0_ISR (void) __irq
    { EXTINT = 0x01;

    IENABLE; TransmitChar0('E');

    Timer1Delay(50); // delay for 50ms sec

    TransmitChar0('I'); TransmitChar0('N'); TransmitChar0('T');

    IDISABLE; VICVectAddr = 0;
    }

    And Timer0 is 10ms.
    After putting IENABLE & IDISABLE.
    processor stop working.

    regards
    SS T.

Children
  • 0 in reply to shyam ST

    I think first u need to disable interrupts when
    u enter ISR, and enable back when u getting out of
    that... anyway also with the defination of your
    IENABLE and IDISABLE macro make sure that u enable
    and disable ONLY current interrupt and remaining interrupts are open.

  • 0 in reply to saurabh p

    I think first u need to disable interrupts when
    u enter ISR

    No. That is the default behavior.

  • 0 in reply to shyam ST

    Timer1Delay(50); // delay for 50ms sec

    why are you doing this?

  • 0 in reply to shyam ST

    if you are transmitting your data using a serial port, why not use the processor's transmit interrupt capability...? or even better, set a hardware timer's overflow counter on such a value that it would generate an interrupt EXACTLY when you need to send data, rather than to wait in the ISR itself?

    you need to:
    * read the processor's manual
    * deepen yourself in the consequences of decisions that you make when you write a program.

  • 0 in reply to Catcus Blip

    There are reasons when an interrupt may need ns or us delays just because the hardware have timing limitations and the delay is too short to allow the next step to be handled by a second interrupt.

    But to have the processor deadlock for 50ms just to delay the transfer of a second character is not good at all. How much do your think your Windows machine would manage to do if all I/O were handled by interrupt service routines performing inter-character delays.

    Always design your ISR to do a quick job and then directly leave. The only reason do to something else is if you for some reason can allow the ISR to permanently lock out the normal program - for example like a trap handler that reports a grave error and then stops the processor in an infinite loop, requiring you to connect with a debugger to check the stack trace.

  • 0 in reply to ImPer Westermark

    Is is possible to interrupt to interrupt isr (timer0 interrupt to ISR of EINT0)?

    SS T.
    Pune India.