I'm having problems with 8051 based ISRs. The problem occures when:
1- Interrupt A is being serviced. 2- Interrupt B occures and is serviced (in the middle of ISR A execution. 3- Sometimes ISR A fails to complete.
I'm using the C ISRs used in C51 without any register set defined ("using xx"). My understanding is that the ISRs should get entered and serviced mutually exclusive from one another without corrupting one another's stack. Is this not the case?
Funny you should mention that trick. I wrote that one up for EDN magazine as a design idea back in about 89 time frame or so. It indeed works. It works because the RETI clears the interrupt disable bit in the hardware and there is no other way to clear it.
The only difference between a RET and a RETI is that one clears the interrupt flag, so you call an RETI and the call puts the value on the stack and the reti returns just like any other return, but also clears the interrupt disable bit.
We used that trick on a very early, OTP 20 pin 8051 when I was working for Eagle Signal Controls in Austin.