Hello
in our sistem we have the necessity to refresh an external Watchdog-Chip, by toggling one OUTPUT-PORT each 160ms. Unfortunately, that must occours also during flash-erasing (...) Well, our bootstrap code makes a copy of both Erase AND Watchdog-Manager code into PSRAM.
This is my code :
HVAR (IO_BYTE, 0xC000AA) = 0x80; HVAR (IO_BYTE, 0xC00054) = 0xAA; HVAR (IO_BYTE, adr) = 0x33; _nop_(); _nop_(); _nop_(); _nop_(); do { FSH_ptrWTD_Process (); //<-manage watchdog-refresh fsreg.v = HVAR (unsigned short,FSR); } while (fsreg.b.busy);
I see that between the excecution of HVAR (IO_BYTE, adr) = 0x33 and the first excecution of FSH_ptrWTD_Process () , there is a delay of about 110 ms, that is the erase timing.
The problem is, that such time could be till 500ms, bigger that our watchdog refreshing time(160ms).
On the Infineon manual xc164_um_v2.1_2004_03_sys.pdf I found " Read accesses to the Flash module are delayed until command mode is terminated."
I am sure that no flash accesses are contained in the watchdog management.
Did I make (see) something wrong or simply there is no chance to avoid this delay?
Data: uP = XC164CS16F20F Model = Medium
Bye and thanks in advance, Federico
Are all other interrupts disabled?
Have you relocated the interrupt table from flash to RAM?
Hallo,
very quick! yes,all interrupts are disabled using
PSW_IEN = 0;
We did not relocated the ISR table.
Maybe is the Flash-erase state machine allocated in flash as well?
Federico
Where is the code to erase the flash located? If it is in the flash (and not the sector you are erasing) then you are stalled until this is finished as the manual states. If you need to service the WDT while erasing the internal flash then I would think you need to execute the erase command sequence from PSRAM or external memory.
"Well, our bootstrap code makes a copy of both Erase AND Watchdog-Manager code into PSRAM."
I can re-formulate the question in this way: during flash-erasing, is the CPU able to excute other commands fething from PSRAM ?
Yes