GPIO

Actually, GPIO on GPIO port 0 and 1 are always enabled. The GPIOM bit of the SCS register just specifies that the new high-speed mode of accessing them should be used for the first two ports, i.e. that the FIO0x and FIO1x registers should be used.

Without setting the GPIO0M bit, the default is that the IO0x and IO1x registers will control the ports.

It is only the first two ports that are controlled by the GPIOM bit - all the other ports are always using the high-speed mode of access.

Actually, GPIO on GPIO port 0 and 1 are always enabled. The GPIOM bit of the SCS register just specifies that the new high-speed mode of accessing them should be used for the first two ports, i.e. that the FIO0x and FIO1x registers should be used.

Without setting the GPIO0M bit, the default is that the IO0x and IO1x registers will control the ports.

It is only the first two ports that are controlled by the GPIOM bit - all the other ports are always using the high-speed mode of access.

Yep, that's what I said. The GPIO ports are not enabled on Bank0 and Bank1 until the GPIOM bit is set. By default at reset the Ports are driven by IOx and FPIOx will not flip a bit.