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How many byte(s)/bits is U8 - char, U16...

This seem just dummy question.

What is a problem. I have some old project, that works on 8 bit prosecos. Now I reforming for arm7 procesor.

Ok, I find out, that in old procesor is int 16 bit type, in arm is 32 bit type, no problem. In rtl.h are definitions like U32 as unsigned int, ... and on the and U8 as unsigned char. Sizeof(U8) is 1 - 1 byte (8 bit).

Than i define my own structure for exaple:

typedef struct
{
    U8   byte_1;
    U16  bytes_2;
} MY_STRUCTURE;

sizeof(MY_STRUCTURE) is 4!!! How could be this posible?

Parents
  • Alignment. The U16 member is 16-bits wide, and so has to start on an even address. Because of this, the compiler has to add a hidden pad byte between byte_1 and bytes_2.

    Most modern microprocessors requires data to be aligned. Some because of the increased speed of getting the data when it is aligned, allowing access with a single memory read, and some because the hardware is totally

    unable to process unaligned integers (other than possibly emulated in an exception handler).

    32-bit processors normally want their 16-bit variables on an even address, and their 32-bit or larger variables to be 4-byte aligned, i.e. have an address with the last two bits zero. Some processors wants (or requires) 64-bit integers, doubles etc to be 8-byte aligned.

    Besides the width of the memory bus, most modern processors also makes use of a processor cache, and the cache is normally way wider than the memory interface, so a cache word may contain two, four or more memory words.

Reply
  • Alignment. The U16 member is 16-bits wide, and so has to start on an even address. Because of this, the compiler has to add a hidden pad byte between byte_1 and bytes_2.

    Most modern microprocessors requires data to be aligned. Some because of the increased speed of getting the data when it is aligned, allowing access with a single memory read, and some because the hardware is totally

    unable to process unaligned integers (other than possibly emulated in an exception handler).

    32-bit processors normally want their 16-bit variables on an even address, and their 32-bit or larger variables to be 4-byte aligned, i.e. have an address with the last two bits zero. Some processors wants (or requires) 64-bit integers, doubles etc to be 8-byte aligned.

    Besides the width of the memory bus, most modern processors also makes use of a processor cache, and the cache is normally way wider than the memory interface, so a cache word may contain two, four or more memory words.

Children