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i am trying to save data in external memory using movx in external memory in the serial interrupt service routine but no data gets saved though when i try storing in data it stores.can i know why and suggest a solution if possible for storing in external memory.enabling the XRAM is done using ALE.Thanks in advance
Using XDATA in an ISR is no different to using it anywhere else.
Does your XDATA work elsewhere in your program?
"enabling the XRAM is done using ALE"
What do you mean by that? There's more to an external memory interface than just ALE.
And are you sure that the software is correctly configured?
"enabling the XRAM is done using ALE" 1) I know of no chip where you can control ALE. 2) if you read/write on the edge of ALE you WILL have problems, what's wrong with using !WR and !RD. 3) xdata problems in an ISR is, typically, related to some switch (e.g. MMIO/memory) in main not considered inside the ISR
Erik
it writes elsewhere but not when the same array is used in the ISR. the processor is recieving data from PC thus requires to have a routine.if i define the same array as data it is capable of storing the recieving the data sent from PC
Can you reproduce this behaviour in the simulator?
how can i send data to the ISR in simulation? is it because of the baudrate i have set it to 38.4kbps. does storing in xdata take a longer time to store when compared to data ,thus not able to store.can we send data to the ISR how i hav not tried that? thanks
"does storing in xdata take a longer time to store when compared to data"
Yes - of course it does! You have the added overhead of handling the DPTR, for a start...
"how can i send data to the ISR in simulation?"
Look-up "Debug Functions" and "Signal Functions" in the simulator manual...
http://www.keil.com/support/man/docs/uv3/ http://www.keil.com/support/man/docs/uv3/uv3_debug_functions.htm http://www.keil.com/support/man/docs/uv3/uv3_simulation.htm
if you set the ISR baudrate to 42.73kbps can you have data stored in xdata faster than idata if idata does not use DPTR with the ISR switched in bank2? i have not tried at 47.32bps but can you do ISR swicth at half code in bank1?
Why did you post that with the 'pre' tags? They are for source code - not text.
All instruction timings for the standard 8051 architecture are given in Chapter 2 of the so-called "bible" for the 8051:
Chapter 2 - 80C51 Family Programmer's Guide and Instruction Set: www.nxp.com/.../80C51_FAM_PROG_GUIDE_1.pdf
If your particular chip differs, you will have to check the appropriate Data Sheet.
You can work it out from there...
You might also do well to check-out the other chapters, for a complete understanding of the 8051 architecture:
Chapter 1 - 80C51 Family Architecture: www.nxp.com/.../80C51_FAM_ARCH_1.pdf
Chapter 3 - 80C51 Family Hardware Description: www.nxp.com/.../80C51_FAM_HARDWARE_1.pdf
Please use the 'Preview' button to check your message before pressing 'Post' - that's what it's there for!
Anyhow, the reply I gave to your first attempt still applies - have you checked-out those documents yet?
if you set the ISR baudrate to 42.73kbps can you have data stored in xdata faster than idata if idata does not use DPTR with the ISR switched in bank2? i have not tried at
47.32bps but can you do ISR swicth at half code in bank1?