Hello, I want to share the external bus interfaces of a ST10F269 and a ST10F276 via the HLDEN-functionality. The pins are connected as follows: ST10F269 <=> ST10F276 D0..D15 <=> D0..D15 A0..A19 <=> A0..A19 /RD <=> /RD /WRL <=> /WRL /WRH <=> /WRH ALE <=> ALE /CS0../CS4 <=> /CS0../CS4 /BREQ <=> /HOLD /HLDA <=> /HLDA /HOLD <=> /BREQ The ST10F269 is configured as follows: - master (DP6.7 = 0) - HLDEN is set - XPERSHARE enabled - XRAM1 (E000-E7FF) enabled - XRAM2 (C000-DFFF) enabled The ST10F276 is configured as follows: - slave (DP6.7 = 1) - HLDEN is set - XPERSHARE disabled - XRAM1 (E000-E7FF) disabled - XRAM2 (F0000-FFFFF) enabled - BUSCON0: 16-Bit demux Now I want to access the master's XRAM (ST10F269) from the slave (ST10F276), /CS0 should get active for these bus accesses. Sometimes I can read correct data out of the master's XRAM, but sometimes I get wrong read data. It seems that bus conflicts occur. Maybe anyone can help me with the following questions: Is it necessary to also enable XPERSHARE in the slave? Is it necessary to enable VISIBLE? Are any waitstates needed for the XRAM access? If the slave (XPERSHARE disabled) accesses his own XRAM, is there also a HOLD-Request generated? Best regards, Michael
This has been tried in vain several times. It can be done, but arbitration is required to avoid both uCs accessing the memory at the same time (when they do, effectively you will get a negative or of the addresses). The problem is, that with the simple schemes that should work, at certain synchronous events (e.g. both requesting acces at the same time or 1 cycle apart) code that seems fine will miss. A circuit I have "inherited" uses about 12 gates and 4 flip-flops for a hardware arbitration and I still have lock outs when debugging. I strongly recommend that you use a dual port memory for this Erik