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We're using AT89C51ED2, and now are busy with a problem, witch was caused by reading back the content of XRAM. As it is officially published in datasheet, this MC has 1792 bytes of internal XRAM. We have set the XRS's bits for selecting the full size of XRAM, and cleared the EXTRAM bit, and EEE bit, mapping the XRAM segment. After that, we are writing data to XRAM using MOVX @DPTR, A procedure. After we have reashed the last adress we are trying to readback the data from XRAM and it is not correct at all.
May be you're right, i'm thinking myself, that it should be stable. I've did not rescaned the reset value, hoping the correct result of reset. I'll try tomorrow do it as you suggest, then will post the result. It is true, that Atmel suggests not to use the R0 registers for accessing the XRAM larger then FFh, but nobody says that it should not work. I'll myself thinking that it will be more reliable to use two registers like R0 and R1, instead of switching between DPTR's. The only thing, that sorrows me is the speed, but in my situation it's not a great problem, and i hope to increase it switching to X2 mode.
It is true, that Atmel suggests not to use the R0 registers for accessing the XRAM larger then FFh, but nobody says that it should not work. Where does the high byte of the address come from? Internal XRAM is - to my knowledge - not attached to P2 in any derivative (it would be ridiculous to do so) I'll myself thinking that it will be more reliable to use two registers like R0 and R1, instead of switching between DPTR's Dual DPTR is not a problem if you pay attention This is not an issue of what is "reliable" but of using the dual DPTR correctly. Erik
"Where does the high byte of the address come from? Internal XRAM is - to my knowledge - not attached to P2 in any derivative (it would be ridiculous to do so)" Don't some variants have an SFR to do this?
hi, It is true, that Atmel suggests not to use the R0 registers for accessing the XRAM larger then FFh, but nobody says that it should not work. You should read the datasheet once again. Thay do say that it does not work: ===== from page 25 of AT89C51RD2 Accesses to XRAM above 0FFH can only be done by the use of DPTR. ===== Notice the word "ONLY" in quotation above. Regards, Oleg
"Where does the high byte of the address come from? Internal XRAM is - to my knowledge - not attached to P2 in any derivative (it would be ridiculous to do so)" Don't some variants have an SFR to do this? yes, most do, but not the derivative discussed. Thus "Where does the high byte ..." Erik