My application needs very fast PEC response times. As i can see in the ".lst" file, the Keil compiler uses EXTS sequences for long addressing memory access: EXTS #014H, #04H MOV R5, [R9] MOV R6, [R9 + #SOF(02H)] MOV R7, [R9 + #SOF(04H)] MOV R8, [R9 + #SOF(06H)] What happens, if a PEC event occurs during the EXTS seqence? Does the PEC transfer interrupt the EXTS Sequence, or is the PEC tranfer delayed until the EXTS sequence is finished?
According to the instruction set manual.
Notes on the ATOMIC and EXTended Instructions These instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR) disable standard and PEC interrupts and class A traps during a sequence of the following 1...4 instructions.