Hello,
I work on a project using the STM32F765. I want to convert a number of adc channels in a sequence, and use DMA2 to transfer the ADC-results into the memory. I didn't find an example in the STM32F7-pack that does exactly what I want, but I was sure that I did modify a similar example correctly. ADC seems to work correctly, DMA seems to fetch the adc-results from the data register, and I got the END OF Conversion irq at the end. But the data were not present at the expected memory area (located in SRAM1).
After many experiments I found a solution: Initially I did not add the DTCM (128kByte starting at 0x2000.0000) in my scatterfile because I wanted to preserve this memory for "critical" tasks. So my memory for DMA transfer was located in SRAM1. As soon as I use memory from DTCM for the DMA-Transfer, everything works as expected.
In the reference manual I read that DMA2 can access the complete memory and I do not find any restrictions (maybe I look at the wrong place..). Could anyone confirm that it is required to use DTCM-memory for peripheral-to-memory DMA transfers? Or does my test indicate that there is another problem in my code because SRAM1 should also work for this DMA transfer? If DTCM-Memory is required for periph=>memory DMA, does anyone know where this is documented?
Thank you.
That would be ST - nothing to do with Keil.
My application is something similar to your application. It would be helpful if you could share the code related to SPI and DMA Initialization.
You sayed:
My application is something similar to your application.
I respondeing:
No. My application is no being liked to the application.
Instead of ADC, I am using Ethernet LAN to read the data. But RX DMA is not working correctly. After DMA reception the values received in SPI DR is always 0xFF. Would you please share your thoughts on this.
my problem was not related to the peripherals. SRAM1/2 is connected to the CPU via an optional cache. If the cache is enabled and DMA changes the memory, the CPU might not see the correct data. User is responsible to make sure the cache is updated before CPU accesses this memory.
If DTCM memory (in my case 0x2000 0000 to 0x2001 FFFF) is used for DMA transfers instead of SRAM1/2 it makes things much easier because DTCM memory is not cached (separate datapath to the CPU).
Thanks for sharing your thoughts. In your earlier post you have mentioned "DMA2 to transfer the ADC-results into the memory." Similarly I am using DMA1 to transfer the LAN (Ethernet packets) - results into the memory. But failed to receive the data into the memory. Memory buffer always contains 0xFF.