Rs485 master-slave communication extra byte reception at slave

Dear experts,
I have a rs485, (lpc1768) master-slave communication setup, that uses uart2 with a gpio line as direction control line.
The experiment is just to test successful communication for transfer of fixed strings.
Master transmits <mastr_addr><slave_addr>HelloWorld.
The slave replies by appending a string RPLY1 to the received string from master, only if the slave addr of the received string matches its own address. This process is looped (in while(1)).
The 1st data transfer from master to slave and back is successful. However, when master transmits the string 2nd time, slave receives an extra 0x00 at the start of the string. This causes slave address byte lag by 1 byte, resulting to slave mismatch.

The receive fifo and transmit fifo are enabled on both master and slave sides, with fifo size of 1 byte only. Baud rate is 115200, 8bit, no parity. communication is interrupt based. Direction control line is functional.

What is the error that causes the extra byte at the start? Is it due to Character time out interrupt? Should i clear the fifo when is start the reception at slave side? How do i solve this?

void RS485UARTx_IRQHandler()
{
        uint32_t irqSrc=0, lnStat=0;
        uint8_t dummy;

        irqSrc = UART_GetIntId(pUart);
        irqSrc &= (UART_IIR_INTID_THRE | UART_IIR_INTID_RDA | UART_IIR_INTID_RLS | UART_IIR_INTID_CTI);             // Only Transmit & Receive Interrupts

        switch(irqSrc)
        {
                case UART_IIR_INTID_RLS:
                        lnStat = pUart->LSR;
                        if(lnStat & (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE ))
                        {
                                dummy = pUart->LSR;
                        }

                        if(lnStat & UART_LSR_RDR)
                        {
                                if(rxRemBytes)
                                {
                                        pRx[rxCnt++] = pUart->RBR;
                                        rxRemBytes--;
                                }
                        }

                        break;

                case UART_IIR_INTID_THRE:
                        if(txRemBytes)
                        {
                                pUart->THR = pTx[txCnt++];

                                txRemBytes--;
                        }
                        else
                        {
                                UART_IntConfig(pUart, UART_INTCFG_THRE, DISABLE);
                        }
                        break;

                case UART_IIR_INTID_RDA:
                        if(rxRemBytes)
                        {
                                pRx[rxCnt++] = pUart->RBR;
                                rxRemBytes--;
                        }
                        else
                        {
                                dummy = pUart->RBR;
                                UART_IntConfig(pUart, UART_INTCFG_RBR, DISABLE);
                                UART_IntConfig(pUart, UART_INTCFG_RLS, DISABLE);
                        }
                        break;

                case UART_IIR_INTID_CTI:
                        dummy = pUart->RBR;
                break;

        }
}