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How to get C51 to generate a DJNZ loop?

I want a fast and simple delay routine:

#pragma OT(8,SPEED)    // Switch to speed optimization for this routine
void my_delay(BYTE count)
{
        register BYTE i;
        for (i=count; i; i--);
}


Is the best so far and becomes:

B02:0xB1F1  EF       MOV      A,R7
B02:0xB1F2  6003     JZ       B02:B1F7
B02:0xB1F4  1F       DEC      R7
B02:0xB1F5  80FA     SJMP     I2C_delay(B02:B1F1)
B02:0xB1F7  22       RET


but I was hoping there was a way to get C51 to do just a DJNZ instead of 4 instructions for each loop.

Is there a magic coding style or optimization level that will generate the DJNZ?

Parents
  • So at least for C51 the pre vs post increment appears to make no difference.

    For that one very limited use, maybe. You're making a mistake if you think that will extend to other situations.

    If you want to control specific opcodes, you'd better look at assembler. Not many compilers allow the control you're looking for.

Reply
  • So at least for C51 the pre vs post increment appears to make no difference.

    For that one very limited use, maybe. You're making a mistake if you think that will extend to other situations.

    If you want to control specific opcodes, you'd better look at assembler. Not many compilers allow the control you're looking for.

Children
  • "even though i and i>0 are the same thing"

    Remember that "i" is the equivalent of "i != 0". And "i > 0" is not the same as "i != 0" unless the specific case of operating on unsigned integers. In this case, Keil seems to have missed an optimization. But then all compilers misses optimizations - it's just a question of how many optimizations they miss.

    Not sure still why you worry about saving instructions in the ms delay. Do you plan to create longer delays by doing multiple calls to this function so a 1% error in the 1ms delay will result in a 10ms error for a 1-second delay?

    You should only do very short delays with instruction-counting in busy-loops. Whenever you need longer delays you should make use of timers or similar. Busy-loop while polling the timer for semi-long delays and make use of interrupts for longer delays.

    The problem with instruction-counting is that it fails to take into account time lost in interrupt handlers - busy-loops with disabled interrupts aren't fun. And any device with some form of interface wants to respond to interface actions without being locked in long delays.

    Instruction-counting delays are best when you need very, very short delays for some setup or hold times. So five "nop" might be enough to have a signal stabilize before performing the next step of some hardware manipulation.

    The difference between pre-, and postincrement relates to the need to make use of the variable value. Post-increment regularly creates a need for a temporary variable with the value before the increment/decrement. In cases where the value isn't used, you would normally get the same performance with both constructs.

  • this thread is missing one very important fact
    delay routines in C are fraught with error opportunities
    the next version of the compiler may do it differently (use DJNZ ?)
    the optimizer may change the code
    ....

    erik

  • Changes to the delay caused by changed compiler version or changed optimization level isn't so much of a problem - code that relies on an instruction-counting busy loop should have some form of benchmark function so normal regression testing can validate the delay.

    What is worse is that global optimization can change the delay after code changes in completely different parts of the code. Because of the problems with supporting high-level languages on the 8051 architecture, you can get parts of the optimization actually happening in the linker. It isn't until linking that variable overlaying can be performed - and first then will it be known the actual address distance between different symbols.

    Making use of a timer means only a changed clock frequency will require code adaptations. So every new release build doesn't require the delay function to be explicitly checked.

  • code that relies on an instruction-counting busy loop should have some form of benchmark function so normal regression testing can validate the delay.
    and you think that will happen?

  • No, I don't. Most people who write busy-loop delays based on execution speed doesn't even realize there are issues with that concept. And neither do they know how to make code testable.

    I just hope that hardware I buy have the code developed by someone who do care and have a reasonable amount of knowledge.

    The big problem is that too much bad code exists on the net - and when people see bad code enough times they tend to assume that it is representative code that represents best practices. People tends to think that if they Google and find an answer, it has to be a good answer - why else would the information show up...