handling of the interrupt enable register in rtx-51

dear all:

In RTX-51 user's guide 09.97 page 25 ,there is a sentence: THE INTERRUPT ENABLE register of the 8051/MCS 251 are managed by RTX-51/251 and must not be directly manipulated by the user!

but look this example :
For example:
#include <rtx51.h>
#include <reg51.h>
#include <stdio.h>

#define STARTUP_TASK 0

//-----------------------------------------------
//-----------------------------------------------
void int0 (void) interrupt 0
{
static unsigned int i;

i++;
}

//-----------------------------------------------
//-----------------------------------------------
void task0 (void) _task_ STARTUP_TASK
{
os_set_slice (1000); /* Set for OSC Frequency / 10,000 */

EX0 = 1; /* Enable External Int 0 */
IT0 = 1; /* Edge-triggered */

os_enable_isr (0); /* Enable interrupt #0 */


while (1)
{
os_wait (K_TMO, 100, NULL);
}
}
//-----------------------------------------------
//-----------------------------------------------
void main (void)
{
os_start_system (STARTUP_TASK);
}

Here why can diretly use "EX0=1"?
What's difference between "EX0=1" and "os_enable_isr(0)"?
Anybody can give me an answer?TKS!

You may download this complete uVision2 application from the following URL:

http://www.keil.com/download/docs/rtx51_ints.zip.asp