FX2 Slave FIFO Manual Mode sample code

Hi ,

Have anybody worked on Cypress FX2 chip. I am writing the firmware for slave FIFO to access the external logic data.
Since my FW has to filter out some data so I have to use AUTOIN =0 mode.
When I see on debug window then I see that I get some of 12-13 bytes packet data ,whearas I am supposed to get 188 bytes of MPEg2 transport stream packet.
I do not know where the problem is.
I am attaching the configuration of All FIFO

Please if anybody has done soemthing like that then please let me know.I will appreciate that.



Rwuen = TRUE; /* Enable remote-wakeup */

/* Configure the FX2 device as Slave FIFO Mode */
CPUCS = 0x10; /* CLKSPD[1:0]=10, for 48MHz operation CLKOE=0, don't drive CLKOUT*/
IFCONFIG = 0xCB; /*IFCONFIG[1:0]=11, FX2 in slave FIFO mode
ASYNC Mode so IFCONFIG.3 =1
IFCONFIG.7 =1 xMHz=1 , internal clk rate
IFCONFIG.6 =1 48MHz
IFCONFIG.5 =0 IFCLKOE=0 , OUTPUT DISBALE FOR ifclk PIN
IFCONFIG.4 IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
*/
/* Configure EndPoint buffers 2/4/6/8, Right now we are configuring the EP2 and EP4 for external Data
transfer from MPEG2 transport stream
*/
REVCTL = 0x03; /*Use enhanced packet handling,Set REVCTL.0=1 and REVCTL.1=1 */
INPKTEND = 0x00; /* Right now only set INPKTEND.7 =1 for SKIP feature */
EP2ISOINPKTS = 0x01; /* For ISO IN Pkt ,01 packet per microframe*/
EP4ISOINPKTS = 0x00; /* Invalid value */
EP6ISOINPKTS = 0x00; /* Invalid value */
EP8ISOINPKTS = 0x00; /* Invalid value */

/* This is commented out because On Power Reset Default Mode for All FIFO's are MANUAL */
EP2FIFOCFG = 0x00; /* EP2FIFOCFG.0 bit =0 for 8 bit FIFO Data Bus.WORDWIDE =0,MANUAL MODE,NO Auto IN */
SYNCDELAY;
EP6FIFOCFG = 0x00; /* EP6FIFOCFG.0 bit =0 for 8 bit FIFO Data Bus.WORDWIDE =0 MANUAL MODE,no AUTO OUT*/
SYNCDELAY;
EP4FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
SYNCDELAY;
EP8FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0

SYNCDELAY;
EP2CFG = 0xDA; /* Valid,IN,Isochronous,1024,double buffer for EP2*/
SYNCDELAY;
EP6CFG = 0x9A; /* Valid,Out,Isochronous,1024,double buffer for EP6*/
SYNCDELAY;
EP4CFG = 0x20; // clear valid bit
SYNCDELAY;
EP8CFG = 0x60; // clear valid bit

SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY;
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY;
SYNCDELAY;
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY;
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY;
FIFORESET = 0x00; // deactivate NAK-ALL

/* setup INT4 as internal source for SlaveFIFO interrupts using INT4CLR (SFR), automatically enabled*/

INTSETUP |= 0x03; // Enable INT4 SlaveFIFO Autovectoring
SYNCDELAY;
EIE |= 0x04; // Enable INT4 ISR, EIE.2=1

SYNCDELAY;
PINFLAGSAB = 0x98; // FLAGA - fixed EP2EF, FLAGB - fixed EP4EF
SYNCDELAY;
PINFLAGSCD = 0xFE; // FLAGC - fixed EP6FF, FLAGD - fixed EP8FF
SYNCDELAY;
PORTACFG |= 0x80; // FLAGD, set alt. func. of PA7 pin
SYNCDELAY;
FIFOPINPOLAR = 0x00; // all signals active low
SYNCDELAY;



Also when I am getting the data ,following is the piece of code

if(( EP24FIFOFLGS & 0x02 ))
{
wByteCount = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL );
printf("No Data -- packets received are = 0x%04x\n",wByteCount);

/* ...EP2EF=1(Flag Empty) it means that there is no data coming from the external logic to the
SlaveFIFO mode i.e. when buffer "empty", no more data to xfr. */
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY;
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY;
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY;
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY;
FIFORESET = 0x00; // deactivate NAK-ALL


}
else /* EP2EF=0, So SlaveFifo is "not empty"*/
{
printf(" Data\n");
/* ...the cpu passed the pkt. to the peripheral domain */
wByteCount1 = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL );

printf("The number of packets received are = 0x%04x\n",wByteCount1);
for (i=0;i<=wByteCount1;i++)
{
bTemp[i] = EP2FIFOBUF[i];
printf("Data Value is= 0x%02bx\n",bTemp[i]);

}

REVCTL = 0x01;
INPKTEND = 0x02; /* INPKTEND.7=1(skip=1) and INPKTEND[1.0] =2(EP2) here FX2 logic automatically ‘dispatches’
an IN buffer, it skips the packet to the USB logic, and writes the accumulated byte
count to the endpoint’s byte count register, thus “arming” the IN transfer.*/


FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY;
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY;
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY;
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY;
FIFORESET = 0x00; // deactivate NAK-ALL


Please help me if anybody has written code for FX2 Slave FIFO In Manual Mode.

Thanks,

Shikha Srivastava