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access to function using absolute addr

Hi,everyone ,I'm trying to access my function using its absolute address.It works when I debug it in KEIL step by step,but it jump to hard fault when runs.
my code is as below:

ptr=(int(*)(int))0x240; //0x240 is the address my function locates.
c=ptr(2);

And I've also met a very similar problem.The program jumps to hard fault when I have function(placed in a single file)placed in a special section .And the placement is fulfilled by sct file like this(fsk_tx.c):

; *************************************************************

LR_IROM1 0x00000000 0x00008000 { ; load region size_region ER_IROM1 0x00000000 0x00007000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO)

} ER_ROM 0x00007000 0X1000 { fsk_tx.o } ER_RAM 0x1FFFFB00 0X100 {

} RW_IRAM1 0x1FFFFD00 0x00000300 { ; RW data .ANY (+RW +ZI) } RW_IRAM2 0x20000000 0x00000C00 { .ANY (+RW +ZI) *(runinram) }
}

And the program works if I comment the fsk_tx.o in the sct file.

I'm really puzzled about it ,and I have to make it work soon.
Thanks !

Parents
  • Not all processors can run code from all addresses - the address range needs to be handled by the prefetch logic.

    Another thing - some processors needs some form of barrier operation after writing code to RAM to make sure that the processor hasn't cached the content of RAM before the RAM write. This can happen when a processor have one instruction cache and one data cache - the data cache sees the RAM writes and has the correct information, but the instruction cache doesn't have any logic to sniff code memory changes.

Reply
  • Not all processors can run code from all addresses - the address range needs to be handled by the prefetch logic.

    Another thing - some processors needs some form of barrier operation after writing code to RAM to make sure that the processor hasn't cached the content of RAM before the RAM write. This can happen when a processor have one instruction cache and one data cache - the data cache sees the RAM writes and has the correct information, but the instruction cache doesn't have any logic to sniff code memory changes.

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