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Since BSRR can perform both set and rest jobs well. Why do we still another 16-bit BRR? I don't understand.
This topic is not really worth extending - but since I have made some mistakes I will extend it a little. Please feel free to ignore any parts as you feel appropriate.
I have mixed some knowledge of STM32F1 hardware parts and STM32F4 hardware parts with some knowledge of the STM32F1 software (.h) and STM32F4 software (.h) and came up with a reality that was not does not fully exist on either one of them.
The STM32F1 parts DO have seperate BSRR and BRR registers. They are in separate address locations - not the same as I said in my previous post. These are both 32-bit registers that need to be written 32-bits at a time. The separate BRR MIGHT be a slight advantage when you only want to reset bits. Give the 16-bits you want to reset, you can write "anything" into the upper 16-bits and it will still only reset the lower 16-bits. So not fully redundant, but redundant enough that so far, I have only used BSRR register even when I only reset bits.
The STM32F4 parts Only have what is called a BSRR register (No BRR), but it can be referenced as 8,16 or 32-bits. This allows you to just write 16-bits and only reset those bits. It adds the ability to write 16-bits to the upper part of the register and only set those bits.
The original STM32F1 .h file gave easy references to both the BSRR and BRR register. They were both 32-bits.
The STM32F4 now only has a BSRR register that behaves exactly like it did before, but has some slightly new capabilities that make what ever the slight benefit of the separate BRR register not exist anymore. So they got rid of the "redundant" BRR. They also "added" the full "benefit" of a seperate BSR (that never existed).
As it appears you have already noticed, the important part is the 32-bit BSRR that allows you to set / reset any combination of values in the GPIO_ODR, changing only the bits you are interested in changing, and also g them all at the same to in either direction. The possibility that in some cases while only resetting bits, it MIGHT be slightly more efficient to write a 32-bit value to a register and have it ignore the upper 16-bit because they contain something other than zero.
typedef struct /* STM32F1 "Software" GPIO Register Definitions*/ { __IO uint32_t CRL; __IO uint32_t CRH; __IO uint32_t IDR; __IO uint32_t ODR; __IO uint32_t BSRR; __IO uint32_t BRR; __IO uint32_t LCKR; } GPIO_TypeDef; typedef struct /* STM32F4 "Software" GPIO Register definitions */ { __IO uint32_t MODER; /*Address offset: 0x00 */ __IO uint32_t OTYPER; /*Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*Address offset: 0x08 */ __IO uint32_t PUPDR; /*Address offset: 0x0C */ __IO uint32_t IDR; /*Address offset: 0x10 */ __IO uint32_t ODR; /*Address offset: 0x14 */ __IO uint16_t BSRRL; /*Address offset: 0x18 */ __IO uint16_t BSRRH; /*Address offset: 0x1A */ __IO uint32_t LCKR; /*Address offset: 0x1C */ __IO uint32_t AFR[2]; /*Address offset: 0x20-0x24 */ } GPIO_TypeDef;
When I said the BSRR and the BRR were the "same register" I was really referring to the F4 part. I define a BSRR that is a uint32_t with an offset of 0x18. This gives me a BSRR that acts just like the BSRR does on the F1 part. The BSRRL and BSRRH add the BRR and BSR capability by overlaying over top of the 32-bit register (BSRRL is (almost) equivalent to the BRR on the F1, but now resides at the same address as the BSRR.