I have code (borrowed from another platform )that attempts to optimize by using assembly code. The function is an addition of arrays and is a C function such as uint32_t AddNumbers ( uint32_t *p_addResult , uint32_t *p_left , uint32_t *p_right , const uint ARRAY_SIZE)
Can I get pointed to a syntax where the passed variables can be assigned to registers and assembly variables.
uint32_t AddNumbers ( uint32_t *p_addResult , uint32_t *p_left , uint32_t *p_right , const uint ARRAY_SIZE) { uint32_t l_counter = ARRAY_SIZE; uint32_t l_carry = 0; uint32_t l_left; uint32_t l_right; __asm( .. "ldmia %[lptr]!, {%[left]} \n\t" "ldmia %[rptr]!, {%[right]} \n\t" "lsrs %[carry], #1 \n\t" "adcs %[left], %[right] \n\t" ... : [dptr] "+l" (p_addResult), [lptr] "+l" (p_left), [rptr] "+l" (p_right), [ctr] "+l" (l_counter), [carry] "+l" (l_carry), [left] "=l" (l_left), [right] "=l" (l_right) }
I am getting syntax errors for the part above that assigns the C variables to registers and assembly variables.
Thanks
So beautifully explained! Thanks !
I think I've gotten a handle of most of it However am trying to wrap my head around some of the pointer to register translation
FunctionCall( ptr 1 , ptr 2 , ptr 3 , size)
Now these are mapped to r0, r1 , r2 and r3 right ?
The first iteration of the loop uses ptr1[0] essentially index 0 I am unable to establish the point where the association between r0 and the next address (ptr + 1 ) occurs.
I see the loop condition being updated but where does the transition from use ptr to using ptr+1 occur?
Thanks!
Take a closer look at the ! used by some of the instructions.
The load and store multiple with ! do the trick, normally they'd do multiple registers, but one works, and the ldr r4, [r1], #4 doesn't work on the M0
ldm r1!, { r4 } ; r4 = *r1++ ldm r2!, { r5 } ; r5 = *r2++ stm r0!, { r4 } ; *r0++ = r4
On function entry r0 = &output[0] (aka output)
I find assembler on the M0 to be significantly more frustrating because so many of the instructions I might have used have been removed. There cores are already very small compared to the RAM, FLASH and PERIPHERALS they are bolted too.