FlashFS NAND K9F5608 not work

...the other always 0xFF.
Thats good. Read the flowchart on page 9 of datasheet. which says:
check 0xff. if not 0xff, then its a bad block.

In Nand flash memory, good memory blocks read 0xff (i.e. all bits of memory locations of good blocks are high)

Read cycle sequence:

wr_cmd(read1_cmd)
set_pageaddr(/* variables*/);
wr_cmd(read2_cmd);    //i cant see this in your code

refer to the timing diagrams given in the datasheet.

what are EMC_ADDR8, EMC_DATA8? what address does it point to?

...the other always 0xFF.
Thats good. Read the flowchart on page 9 of datasheet. which says:
check 0xff. if not 0xff, then its a bad block.

In Nand flash memory, good memory blocks read 0xff (i.e. all bits of memory locations of good blocks are high)

Read cycle sequence:

wr_cmd(read1_cmd)
set_pageaddr(/* variables*/);
wr_cmd(read2_cmd);    //i cant see this in your code

refer to the timing diagrams given in the datasheet.

what are EMC_ADDR8, EMC_DATA8? what address does it point to?

The second read command does not exist on the command table (page 4).
I found it strange, but it seems that the sequence of reading is just cmd and addr

EMC defs:

#define K9F5608_HDW_CS          0x01

#define EMC_NAND_BASE           (0x80000000 + 0x1000000 * K9F5608_HDW_CS)
#define EMC_ALE_ADDR            0x00080000
#define EMC_CLE_ADDR            0x00100000
#define EMC_DATA8               *((volatile U8 *)(EMC_NAND_BASE))
#define EMC_ADDR8               *((volatile U8 *)(EMC_NAND_BASE + EMC_ALE_ADDR))
#define EMC_CMD8                *((volatile U8 *)(EMC_NAND_BASE + EMC_CLE_ADDR))

The second read command does not exist on the command table
obviously there is. Check and recheck (refer the datasheet of the link)

and follow the timing diagram of the read sequence.

Still nothing..
What I found was 0x00 or 0x01 and 3 cycles of address.. RB wait and read the data..

on page 13 of datasheet watch the IO 0-7 lines.
it shows that you have to send 4 address cycles (irrespective of whether the 1st cycle is 0x00 or 0x01).

WrCmd (NAND_CMD_READ1ST);               // Write Read command Byte1

SetPgAddr (AddrCycles, row, PageSize);  // Set address

WrCmd (NAND_CMD_READ2ND);               // Write Read command Byte2
EMC_ADDR8 = 0;

for(i=1000;i;i--);

if( WaitReady() == NAND_BUSY)           // Wait until NAND ready
{
        return ERR_NAND_HW_TOUT;
}


...//read data

Dont you have example codes for nand flash interface with LPC2478?
have you tried executing those codes?

For memory K9F1G08 has examples and works. This memory has 2 commands for reading and 4 address cycles.

WrCmd (NAND_CMD_READ1ST);                        // 0x00
SetPgAddr (cfg->AddrCycles, row, cfg->PageSize); // 4 cycles
WrCmd (NAND_CMD_READ2ND);                        // 0x30
WaitReady();                                     // busy

The memory I'm using is K9F5608, this does not have specific examples for LPC2478. This memory has only 1 read command and 3 address cycles.

WrCmd (NAND_CMD_READ1HALF);                      // 0x00 or 0x01 (1º half or 2º half)
SetPgAddr (cfg->AddrCycles, row, cfg->PageSize); // 3 cycles
WaitReady();                                     // busy

I can run the commands read id, read status, reset..
However the commands for reading and writing the page does not work correctly.
For example, in reading the page the first byte read is always equal to the last data byte from the previous command, the others are always 0xFF.

The write command can not say it works because it does not work the command to read the data..