This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

XE166: Can't clear SCU's system timer interrupt

Hi,

I'm on a XE160 and trying to use the SCU's system timer STM - clocked from the wake-up clock - as a constant time base while changing PLL settings. System also runs from the wake-up clock at that time.

In this instance of usage I simply want to poll until 200µs elapsed. This is what I do:

   SCU_INTDIS = 0x3ECF;
   SCU_STMCON = 0x00;

   ...

   SCU_STMREL = 0x10000 - 100;                    /* Wait for 100 * 2µs */
   SCU_STMCON = 0x01;                             /* Reload and run STM */
   for (SCU_DMPMITCLR = 0x0400; ((SCU_DMPMIT >> 10) & 0x01) == 0; );
   SCU_STMCON = 0x00;                             /* Stop it */


So, in the for() statement I set the STM1I bit in DMPMITCLR which is supposed to clear the corresponding bit in DMPMIT, and wait until the bit gets set again, which would indicate that the set timer period elapsed and the timer overflowed. I observe however that no waiting is happening: After execution of the "DMPMITCLR = 0x0400" the corresponding bit in DMPMIT does not get cleared. Or - as I suspect - it gets set again immediately. On SCU interrupts, the manual says:

--------8<--------8<--------
Note: When servicing an SCU interrupt request, make sure that all related request flags
are cleared after the identified request has been handled. To clear an interrupt
request that is stored in register DMPMIT, first clear the request source of the
source (e.g. WUTRG), clear the request within DMP_M via DMPMITCLR
, and
then clear the request via INTCLR. (Page 8-170 in xe166u_um_v1.1_2011_03.pdf)
--------8<--------8<--------

So it behaves just as if the "request source" is not "cleared". Trouble is: the manual does not document any request source for the two system timer interrupts. There is nothing like the WUTRG bit for the system timer interrupts. Or is there?

Cheers Peter

Parents
  • Fixed.

    It's a quirk about the hardware that Infineon did not exactly go out of their way to document.
    The DMPMIT bit cannot be cleared while the timer is running. Why this is the case is a complete mystery for me, but Infineon could at least have mentioned it in the manual. But they didn't :-(

    Cheers Peter

Reply
  • Fixed.

    It's a quirk about the hardware that Infineon did not exactly go out of their way to document.
    The DMPMIT bit cannot be cleared while the timer is running. Why this is the case is a complete mystery for me, but Infineon could at least have mentioned it in the manual. But they didn't :-(

    Cheers Peter

Children
No data