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Hardware cause for "Cannot Write to RAM for Flash Algorithms" error?

I am using MDK-Lite Version: 5.11.0.0 with a ULink ME (V2.02) to develop code on an ADuc7021 32K part. I have two versions of hardware that have identical JTag circuitry with slightly differing processor IO. One board programs and verifies without problems, and the other fails with "Cannot Write to RAM for Flash Algorithms !" errors. The debug and RAM setup is correct for the device. I have searched for solutions, but the only guidance I can find suggests altering the debug and JTag setup or the device RAM settings which I know are correct. The problem can only be a hardware issue, but having compared the JTag on working and non-working boards, signal for signal, level for level, I have reached a point where I cannot progress further.

Do you know of any issues that would cause "Cannot Write to RAM for Flash Algorithms !" when all the RAM and debug settings are correct?

Regards,
Kristin Hansen, Senior Development Engineer

Parents
  • Do you have any other JTAG test gear, can you do a boundary scan of the device. Sorry not intimately familiar with the AD family of devices.

    Would double check schematic and PCB. Check pull-up resistors, and any potential cross-connectivity on the JTAG pins (TDI, TDO, TMS, RST, TCK, etc). Ground pads? Check an unpopulated board (solder test) for continuity.

    Is your manufacturing group capable of X-Raying the board to look for under chip soldering issues?

Reply
  • Do you have any other JTAG test gear, can you do a boundary scan of the device. Sorry not intimately familiar with the AD family of devices.

    Would double check schematic and PCB. Check pull-up resistors, and any potential cross-connectivity on the JTAG pins (TDI, TDO, TMS, RST, TCK, etc). Ground pads? Check an unpopulated board (solder test) for continuity.

    Is your manufacturing group capable of X-Raying the board to look for under chip soldering issues?

Children
  • Found it!

    One of the new GPIO outputs (swapped from a DAC output on first prototype) was to activate a circuit to trigger Bootmode on reset. This wasn't immediately apparent as the Bootmode input pin was measured at high level when unprogrammed (default settings?). However, when #RST was triggered by JTAG, the bootmode input was held low for the duration of reset – hence entering Bootmode and stopping JTAG.

    Definite Face-Palm moment.

    Thanks for your help.