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Non-aligned Access: ARM Instruction at XXX, Memory Access at YYY

Terje Bohler

Hi.

I get the following error during runtime (after 8 sec run):
"Non-aligned Access: ARM Instruction at 001042F8H, Memory Access at 00000001H
Data Abort: ARM Instruction at 001042F8H, Memory Access at 00000001H"

The failing code contain debug code:

. . .
unsigned int *dbgPinX, *dbgPin11 ...
. . .
if(ch & 0x01)
{
  dbgPin11 = (unsigned int *)(pinsOledData+i);  // for IO
  if (dbgPin11 > (unsigned int *)0x200000)
    dbgX=2;
  else
    dbgX=1;
 dbgPinX = dbgPin11; // THIS LINE CAUSE THE ERROR !!!

 ((pinsOledData+i)->pio)->PIO_SODR = (pinsOledData+i)->mask;
}
. . .


The statement in question is executed lots of times, but 8 sec after each program-start, this statement will fail (every run), with the above mentioned error-message !

If anyone can give me a clue, I'll apreciate that very much.

Regards Terje Bøhler

Parents
  • 0 in reply to ImPer Westermark

    Hi.

    Problem solved.
    The code (which by the way was written by another programmer) was originally written under another IDE. I'm currently in the prosess of converting it to KEIL. So, here is the problem/solution:
    Originally written Interrup Service Routines (handlers) were by default named ISR_XXX.
    This would caused the local/old IDE's compiler to automatically treat it as an interrupt service routine, and add the required register bank switching at entry/exit.
    Under KEIL, another mechanism is used: Procedures are to be called XXX()__irq() to acheive register bank switching. So, the following happend:
    When the 1st interrupt occurred, at exit from the ISR, the registers contained "random values" (from the ISR) and hence, program failed ... simple as that ...

    Regards Terje

Reply
  • 0 in reply to ImPer Westermark

    Hi.

    Problem solved.
    The code (which by the way was written by another programmer) was originally written under another IDE. I'm currently in the prosess of converting it to KEIL. So, here is the problem/solution:
    Originally written Interrup Service Routines (handlers) were by default named ISR_XXX.
    This would caused the local/old IDE's compiler to automatically treat it as an interrupt service routine, and add the required register bank switching at entry/exit.
    Under KEIL, another mechanism is used: Procedures are to be called XXX()__irq() to acheive register bank switching. So, the following happend:
    When the 1st interrupt occurred, at exit from the ISR, the registers contained "random values" (from the ISR) and hence, program failed ... simple as that ...

    Regards Terje

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