• State Not Answered
  • Locked Locked
  • Replies 4 replies
  • Subscribers 22 subscribers
  • Views 1400 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

FGPIO - high Impedance during power up

Ravi sankar

Hi, I would be glad if any one can help me how to change the default high impedance state during reset/powering up of my LPC 2468 MCU. I want to make them logic 0(LOW) till I change the state in the code. My specific application is to give the o/p of GPIOs to IDT74ALVC164245PAG8 which considers high impedance of GPIOs as high (mistakenly) which eventually turns ON some special relays,which is destroying my end application.

Any help from experienced users would be appreciated.

Thanks in advance.

Parents
  • 0 in reply to ImPer Westermark

    Dear Mr. Per Westermark,

    Thanks for your reply. However the PCB is already fabricated and we could not find the problem in design phase. What I request you is, is there any way in the code or in 'ini' file to drive the pins logic low during and after boot/ power up until I drive GPIOs to logic high in the code? i.e any command to be changed in the boot code/ini file to do so?

    Thanks in advance.

Reply
  • 0 in reply to ImPer Westermark

    Dear Mr. Per Westermark,

    Thanks for your reply. However the PCB is already fabricated and we could not find the problem in design phase. What I request you is, is there any way in the code or in 'ini' file to drive the pins logic low during and after boot/ power up until I drive GPIOs to logic high in the code? i.e any command to be changed in the boot code/ini file to do so?

    Thanks in advance.

Children
  • 0 in reply to Ravi sankar

    You aren't in control of the pins while the processor is in the reset state.
    So the only way to force them low on reset is to use external pull-down.

    That is a very big reason why the pin states at reset (every used pin) should be part of a very carefully processed check list to make sure that the hardware design will be able to perform as excepted both when the application software is in control, when the processor is powering up, and when the processor is fully powered but hanging in the reset state.

    Lots of processors do not have any 'fuse' settings where it's possible to program them to know if I/O pins should be high or low or tristate during reset. That is why so many processors selects to be either tristate or use a very weak pull-up or pull-down, to allow the hardware designers to be able to add resistors to take care of the time when the processor firmware isn't in control.

  • 0 in reply to ImPer Westermark

    Hi,

    Thanks for the solution. However somehow we managed to achieve this. We have changed the direction of IDT level converter from Output to Input mode using some pull down resistors of about 500 ohm. After the processor boots up, the direction has been changed from Input to Output mode in the software. Our problem has been solved.