Suppose I an writing a single pin repeatedly like:
LPC_GPIO->SET[0] = 1; LPC_GPIO->SET[0] = 0; LPC_GPIO->SET[0] = 1; LPC_GPIO->SET[0] = 0; // interrupt comes here LPC_GPIO->SET[0] = 1; LPC_GPIO->SET[0] = 0;
If no optimization is used then all instruction will be converted into load, mov & store. Load, mov & store is atomic so cannot be interrupted.
Bit if I use optimization, then compiler will load address on first line only & then it keep STROE instruction only for rest of instruction as address has already been loaded.
What if now interrupt comes as I marked & in interrupt some other address register is loaded. When control comes out of ISR , what will happen as new address has been loaded