I recently had a problem with some production units refusing to program using a ULINK2.
The processors involved are ARM7 NXP devices and scoping the activity on the JTAG bus it appears the problem was that at the point where data starts to appear on the TDI, TDO and TMS lines the processors in question may have still been in reset. Some were OK others were not.
The ULINK pulls the reset line low for about 40ms releases it waits about 260ms then there is activity on the JTAG lines. It pulls the reset line low again for another 40ms or so, releases it and there is activity on the JTAG lines after about 3.2ms.
I appear to have fixed my problem by speeding up coming out of reset when the JTAG pulls the reset line low but I have not been able to find any documentation on JTAG timing with the ULINK2 to be sure I have now have a design that will always work.
I'm looking for figures on the maximum time the ULINK2 can pull the RESET line low for and the minimum time after releasing RESET before the processor should be out of reset and ready to handle JTAG activity. Is there any document that provides this information, and if so can you please provide me with a link?