Hello All,
Does the Boards have an onboard static RAM ? If NOT then how can the processor make any CALL,PUSH or service INTERRUPTs ? Now a days i do not see any STATIC RAM chip on the boards.(Is it built into any kind of chipset) What is going on,i do not understand how a processor can work without STATIC RAM ?
And i assume that now boards have started using serial SPI FLASH chips for stuff instead of parallel one. Does it mean that processor has special circuitry inbuilt to read and execute in place (XIP) from serial FLASH chips.
Where to get complete standard specification for the boards,if i want to program the memory chip with my own OS.
Does the Boards have an onboard static RAM ?
all I know of do; however, as the amount of RAM internal to the uC chip is increasing, more and more (for ARM all demo/eval boards I know of) get by with the RAM internal to the uC chip. just as an example the board I am currently using the FDDM-KL25Z is using a chip with 128 KB flash and 16 KB SRAM
Erik
Even "big" processors are starting to have flash and RAM internally, which allows them to run boot loaders and perform self-tests with zero external memory functioning. The availability of executable RAM inside the chip does wonders for your abilities to play with a JTAG interface.
This also allows them to use encryption and/or authentication when loading secondary software, with the cryptographic key locked up inside the processor.
By the way - why you use the term "static" about the RAM? Just that a device have RAM doesn't give us any insight into the actual memory technology.
Just like the existence of flash memory can't be assumed to be serial. Serial flash are normally external flash accessed "like a hard disk" for loading code into RAM before execution, while internal flash memories are normally parallel to allow running of code directly from the internal flash.
The main reason for serial flashes is their much lower requirements on number of pins - that is irrelevant when the memory is inside the processor. Internally, you can just as well have a 256-bit wide memory bus if the core is so fast that it can actually consume data fast enough to need panic-loads of the cache lines.
But random discussions about random memory implementations for random processors is quite irrelevant. You normally have a specific problem to solve, in which case you look for a suitable processor well mapped to that problem. Or you happen to have some new hardware, and instead wants to figure out what new things you can do with this hardware - potentially break into new markets because of a novel product or a significant performance or cost improvement.