i am using K9F1G08U0B, and interface with LPC2468 micorcontroller, i am writing 5 pages data, when i am reading 5 pages data only first two pages data will be display correct remaining pages are displayed wrong data(i.e first data, second data, first data).
how to read multiple pages in K9F1G08U0B
I am using SDRAM IC K4S561632H when ever run my code 0xFF 0xFF 0xFF 0xFF...... are coming in dynamic address is 0xA0000000
my source code is
sdram.c
void SDRAMInit( void ) { DWORD i, dummy = dummy; // SCS |= 0x00000002; /* Reset EMC */ EMC_CTRL = 0x00000001; /*Disable Address mirror*/ PCONP |= 0x00000800; /* Turn On EMC PCLK */ PINSEL4 = 0x50000000; PINSEL5 = 0x05050555; PINSEL6 = 0x55555555; PINSEL8 = 0x55555555; PINSEL9 = 0x50555555; EMC_DYN_RP = 2; /* command period: 3(n+1) clock cycles */ EMC_DYN_RAS = 3; /* RAS command period: 4(n+1) clock cycles */ EMC_DYN_SREX = 7; /* Self-refresh period: 8(n+1) clock cycles */ EMC_DYN_APR = 2; /* Data out to active: 3(n+1) clock cycles */ EMC_DYN_DAL = 5; /* Data in to active: 5(n+1) clock cycles */ EMC_DYN_WR = 1; /* Write recovery: 2(n+1) clock cycles */ EMC_DYN_RC = 5; /* Active to Active cmd: 6(n+1) clock cycles */ EMC_DYN_RFC = 5; /* Auto-refresh: 6(n+1) clock cycles */ EMC_DYN_XSR = 7; /* Exit self-refresh: 8(n+1) clock cycles */ EMC_DYN_RRD = 1; /* Active bank A->B: 2(n+1) clock cycles */ EMC_DYN_MRD = 2; /* Load Mode to Active cmd: 3(n+1) clock cycles */ EMC_DYN_RD_CFG = 1; /* Command delayed strategy */ /* Default setting, RAS latency 3 CCLKs, CAS latenty 3 CCLKs. */ EMC_DYN_RASCAS0 = 0x00000303; #if ENG_BOARD_LPC24XX /* NXP engineering board */ /* 256MB, 16Mx16, 4 banks, row=12, column=9 */ EMC_DYN_CFG0 = 0x00000480; #else /* Embedded Artists board */ /* 256MB, 16Mx16, 4 banks, row=13, column=9 */ EMC_DYN_CFG0 = 0x00000680; #endif delayMs(1, 100); /* use timer 1 */ /* Mem clock enable, CLKOUT runs, send command: NOP */ EMC_DYN_CTRL = 0x00000183; delayMs(1, 200); /* use timer 1 */ /* Send command: PRECHARGE-ALL, shortest possible refresh period */ EMC_DYN_CTRL = 0x00000103; /* set 32 CCLKs between SDRAM refresh cycles */ EMC_DYN_RFSH = 0x00000002; for(i = 0; i < 0x40; i++); /* wait 128 AHB clock cycles */ /* set 28 x 16CCLKs=448CCLK=7us between SDRAM refresh cycles */ EMC_DYN_RFSH = 28; /* To set mode register in SDRAM, enter mode by issue MODE command, after finishing, bailout and back to NORMAL mode. */ /* Mem clock enable, CLKOUT runs, send command: MODE */ EMC_DYN_CTRL = 0x00000083; /* Set mode register in SDRAM */ /* Mode regitster table for Micron's MT48LCxx */ /* bit 9: Programmed burst length(0) bit 8~7: Normal mode(0) bit 6~4: CAS latency 3 bit 3: Sequential(0) bit 2~0: Burst length is 8 row position is 12 */ dummy = *((volatile DWORD *)(SDRAM_BASE_ADDR | (0x33 << 12))); EMC_DYN_CTRL = 0x00000000; /* Send command: NORMAL */ EMC_DYN_CFG0 |= 0x00080000; /* Enable buffer */ delayMs(1, 1); /* Use timer 1 */ return; }
main.c
SDRAMInit(); wr_ptr = (DWORD *)SDRAM_BASE_ADDR; char_wr_ptr = (BYTE *)wr_ptr; for ( i= 0; i < SDRAM_SIZE/4; i++ ) { *wr_ptr++ = 0; } //8 bit write for (i=0; i<SDRAM_SIZE; i++) { *char_wr_ptr++ = 0xAA; *char_wr_ptr++ = 0x55; *char_wr_ptr++ = 0x5A; *char_wr_ptr++ = 0xA5; }
Have you done some basic checking of the hardware, can confirmed your can see clock, ras, cas signals on the appropriate pins?
In your first post you said, "i am using K9F1G08U0B";
In your latest post you said, "I am using SDRAM IC K4S561632H";
Your code says,
/* Mode regitster table for Micron's MT48LCxx */
So which is it?
K9F1G08U0B problem solved.
Now i am testing K4S561632H
So why using code for MT48LCxx ?
K9F1G08U0B is a Parallel Non-Volatile Flash memory K4S561632H is a Parallel SDRAM (needless to say, is volatile).
K9F1G08U0B problem solved. did u figure out the exact problem? what was the solution?