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Un able to access the registers of XMC4500 with Kiel

This is my Intialization for Configuring SPI of XMC4500 Relax kit lite with keil Development Environment, It does not use Dave apps. When i Debug the Program by calling the Function to Main Not even One Register In the USIC1_CH1 channel has been Configured, Every Register in USIC1_CH1 is set to or confined to the same value 0xffff. Is there a Linker script problem or Something I need to do special to access the Registers using keil?

#include <XMC4500.h>

void SPI_config( void )
{
        // Disable SPI
        //USIC1_CH1->CCR &= ~( ((uint32_t)(0x01U & USIC_CH_CCR_MODE_Msk)));

        // Enable SPI
        USIC1_CH1->CCR |= 0x0001;


        // Switch off the Baud rate generation
        USIC1_CH1->FDR=0;
        USIC1_CH1->BRG=0;


        // For Full duplex Configuration
         USIC1_CH1->DX0CR |= (((1U << USIC_CH_DX0CR_INSW_Pos) & \ 
        USIC_CH_DX0CR_INSW_Msk));


        // HPCEN is Diabled
        USIC1_CH1->CCR |= ((0U << USIC_CH_CCR_HPCEN_Pos) & \ 
                                                         USIC_CH_CCR_HPCEN_Msk);


         /* Configuration of Protocol Control Register */
  USIC1_CH1->PCR_SSCMode |=
     (((0x00U & USIC_CH_PCR_SSCMode_MSLSEN_Msk)) | \ 
         ((0U << USIC_CH_PCR_SSCMode_SELCTR_Pos) & \ 
             USIC_CH_PCR_SSCMode_SELCTR_Msk) | \ 
             ((0U << USIC_CH_PCR_SSCMode_SELINV_Pos) & \ 
             USIC_CH_PCR_SSCMode_SELINV_Msk) | \ 
             ((0U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos) & \ 
             USIC_CH_PCR_SSCMode_CTQSEL1_Msk) | \ 
             ((0U << USIC_CH_PCR_SSCMode_PCTQ1_Pos) & \ 
             USIC_CH_PCR_SSCMode_PCTQ1_Msk) | \ 
             ((0U << USIC_CH_PCR_SSCMode_DCTQ1_Pos) & \ 
             USIC_CH_PCR_SSCMode_DCTQ1_Msk) | \ 
             ((0U << USIC_CH_PCR_SSCMode_MSLSIEN_Pos) & \ 
             USIC_CH_PCR_SSCMode_MSLSIEN_Msk) | \ 
             ((0U << USIC_CH_PCR_SSCMode_SELO_Pos) & \ 
             USIC_CH_PCR_SSCMode_SELO_Msk) | \ 
             ((0U << USIC_CH_PCR_SSCMode_TIWEN_Pos) \ 
             & USIC_CH_PCR_SSCMode_TIWEN_Msk));


         /* Configuration of USIC Shift Control */
    USIC1_CH1->SCTR &= \ 
    (~(uint32_t)(USIC_CH_SCTR_SDIR_Msk | USIC_CH_SCTR_FLE_Msk | \ 
                  USIC_CH_SCTR_WLE_Msk | USIC_CH_SCTR_HPCDIR_Msk | \ 
         USIC_CH_SCTR_DSM_Msk));


  /* Configuration of USIC Shift Control */
  USIC1_CH1->SCTR |= \ 
     (((1U  <<  USIC_CH_SCTR_PDL_Pos ) & \ 
     USIC_CH_SCTR_PDL_Msk ) | \ 
     ((1U <<  USIC_CH_SCTR_TRM_Pos ) & \ 
     USIC_CH_SCTR_TRM_Msk ) | \ 
      (((FrameLen - 1U) << USIC_CH_SCTR_FLE_Pos)\ 
      & USIC_CH_SCTR_FLE_Msk ) | \ 
      (((WordLen - 1U) << USIC_CH_SCTR_WLE_Pos) \ 
      &  USIC_CH_SCTR_WLE_Msk));



        // DX0D is selected /* Configure P0.0 MTSR / U1C1.DX0D */
        WR_REG(USIC1_CH1->DX0CR, (uint32_t)USIC_CH_DX0CR_DSEL_Msk, \ 
                         USIC_CH_DX0CR_DSEL_Pos,(uint32_t)3);


        /* Configure P0.10, CLKIN (U1C1.DX1A) */
        USIC1_CH1->DX1CR =
                        (0 << USIC_CH_DX1CR_DSEL_Pos)     |       // DX1A is selected
                        (1 << USIC_CH_DX1CR_INSW_Pos)     |
                        (0 << USIC_CH_DX1CR_DFEN_Pos)     |
                        (0 << USIC_CH_DX1CR_DSEN_Pos)     |
                        (0 << USIC_CH_DX1CR_DPOL_Pos)     |
                        (0 << USIC_CH_DX1CR_SFSEL_Pos)    |
                        (0 << USIC_CH_DX1CR_CM_Pos)               |
                        (0 << USIC_CH_DX1CR_DXS_Pos)      ;


        /* Configure P0.9, CS (U1C1.DX2A) Chip select */
        USIC1_CH1->DX2CR =
                        (0 << USIC_CH_DX2CR_DSEL_Pos)     |       // DX2A is selected
                        (1 << USIC_CH_DX2CR_INSW_Pos)     |
                        (0 << USIC_CH_DX2CR_DFEN_Pos)     |
                        (0 << USIC_CH_DX2CR_DSEN_Pos)     |
                        (0 << USIC_CH_DX2CR_DPOL_Pos)     |
                        (0 << USIC_CH_DX2CR_SFSEL_Pos)    |
                        (0 << USIC_CH_DX2CR_CM_Pos)               |
                        (0 << USIC_CH_DX2CR_DXS_Pos)      ;


        /* Control P0.10 as  Clock Input pin, Strong drive strength */
        PORT0->IOCR8 = (PORT0->IOCR8 & ~ 0xF80000) | (0 << 19);
        PORT0->PDR1 = (PORT0->PDR1 & ~0x700) | (2 << 8);

        /* Control P0.9 as Chip select Input pin, Strong drive strength */
        PORT1->IOCR8 = (PORT1->IOCR8 & ~0xF800) | (0 << 11);
        PORT1->PDR1 = (PORT1->PDR1 & ~0x70) | (2 << 4);

        /* Control P0.0 MTSR as Input pin, Strong drive strength */
        PORT1->IOCR0 = (PORT1->IOCR0 & ~0xF8) | (0 << 3);
        PORT1->PDR0 = (PORT1->PDR0 & ~0x7) | (2 << 0);


    USIC1_CH1->CCR |= (((uint32_t)(1U & USIC_CH_CCR_MODE_Msk)));

}