line 3: Mode_USR EQU 0x10 line 4: Mode_FIQ EQU 0x11 Mode_IRQ EQU 0x12 Mode_SVC EQU 0x13 Mode_ABT EQU 0x17 Mode_UND EQU 0x1B Mode_SYS EQU 0x1F
I_Bit EQU 0x80 F_Bit EQU 0x40
UND_Stack_Size EQU 0x00000004 SVC_Stack_Size EQU 0x00000004 ABT_Stack_Size EQU 0x00000004 FIQ_Stack_Size EQU 0x00000004 IRQ_Stack_Size EQU 0x00000080 USR_Stack_Size EQU 0x00000400
AREA STACK, DATA, READWRITE, ALIGN=2 DS (USR_Stack_Size+3)&~3 DS (SVC_Stack_Size+3)&~3 DS (IRQ_Stack_Size+3)&~3 DS (FIQ_Stack_Size+3)&~3 DS (ABT_Stack_Size+3)&~3 DS (UND_Stack_Size+3)&~3
line 30:Top_Stack:
// VPBDIV definitions VPBDIV EQU 0xE01FC100
VPBDIV_SETUP EQU 1 VPBDIV_Val EQU 0x00000001
// Phase Locked Loop (PLL) definitions PLL_BASE EQU 0xE01FC080 PLLCON_OFS EQU 0x00 PLLCFG_OFS EQU 0x04 PLLSTAT_OFS EQU 0x08 PLLFEED_OFS EQU 0x0C PLLCON_PLLE EQU (1<<0) PLLCON_PLLC EQU (1<<1) PLLCFG_MSEL EQU (0x1F<<0) PLLCFG_PSEL EQU (0x03<<5) PLLSTAT_PLOCK EQU (1<<10)
PLL_SETUP EQU 1 PLLCFG_Val EQU 0x00000024
// Memory Accelerator Module (MAM) definitions MAM_BASE EQU 0xE01FC000 MAMCR_OFS EQU 0x00 MAMTIM_OFS EQU 0x04
MAM_SETUP EQU 1 MAMCR_Val EQU 0x00000002 MAMTIM_Val EQU 0x00000004
// Starupt Code must be linked first at Address at which it expects to run.
$IF (EXTMEM_MODE) CODE_BASE EQU 0x80000000 $ELSEIF (RAM_MODE) CODE_BASE EQU 0x40000000 $ELSE CODE_BASE EQU 0x00000000 $ENDIF
AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4 PUBLIC __startup
EXTERN CODE32 (?C?INIT)
__startup PROC CODE32
EXTERN CODE32 (Undef_Handler?A) EXTERN CODE32 (SWI_Handler?A) EXTERN CODE32 (PAbt_Handler?A) EXTERN CODE32 (DAbt_Handler?A) EXTERN CODE32 (IRQ_Handler?A) EXTERN CODE32 (FIQ_Handler?A)
Vectors: LDR PC,Reset_Addr LDR PC,Undef_Addr LDR PC,SWI_Addr LDR PC,PAbt_Addr LDR PC,DAbt_Addr NOP ; LDR PC,IRQ_Addr LDR PC,[PC, #-0x0FF0] LDR PC,FIQ_Addr
Reset_Addr: DD Reset_Handler Undef_Addr: DD Undef_Handler?A SWI_Addr: DD SWI_Handler?A PAbt_Addr: DD PAbt_Handler?A DAbt_Addr: DD DAbt_Handler?A DD 0 IRQ_Addr: DD IRQ_Handler?A FIQ_Addr: DD FIQ_Handler?A
Reset_Handler:
IF (VPBDIV_SETUP != 0) LDR R0, =VPBDIV LDR R1, =VPBDIV_Val STR R1, [R0] ENDIF
IF (PLL_SETUP != 0) LDR R0, =PLL_BASE MOV R1, #0xAA MOV R2, #0x55
// Configure and Enable PLL MOV R3, #PLLCFG_Val STR R3, [R0, #PLLCFG_OFS] MOV R3, #PLLCON_PLLE STR R3, [R0, #PLLCON_OFS] STR R1, [R0, #PLLFEED_OFS] STR R2, [R0, #PLLFEED_OFS]
// Wait until PLL Locked PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS] ANDS R3, R3, #PLLSTAT_PLOCK BEQ PLL_Loop
// Switch to PLL Clock MOV R3, #(PLLCON_PLLE | PLLCON_PLLC) STR R3, [R0, #PLLCON_OFS] STR R1, [R0, #PLLFEED_OFS] STR R2, [R0, #PLLFEED_OFS] ENDIF
IF (MAM_SETUP != 0) LDR R0, =MAM_BASE MOV R1, #MAMTIM_Val STR R1, [R0, #MAMTIM_OFS] MOV R1, #MAMCR_Val STR R1, [R0, #MAMCR_OFS] ENDIF
// Memory Mapping MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */
$IF (REMAP) LDR R0, =MEMMAP $IF (EXTMEM_MODE) MOV R1, #3 $ELSEIF (RAM_MODE) MOV R1, #2 $ELSE MOV R1, #1 $ENDIF STR R1, [R0] $ENDIF
// Setup Stack for each mode LDR R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND|I_Bit|F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size
// Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR MOV SP, R0
// Enter the C code LDR R0,=?C?INIT TST R0,#1 ; Bit-0 set: INIT is Thumb LDREQ LR,=exit?A ; ARM Mode LDRNE LR,=exit?T ; Thumb Mode BX R0 ENDP
PUBLIC exit?A exit?A PROC CODE32 B exit?A ENDP
PUBLIC exit?T exit?T PROC CODE16 exit: B exit?T ENDP
END
this is the start up file Startup.s(3): error: A1163E: Unknown opcode Mode_USR , expecting opcode or Macro Startup.s: 3 00000000 Mode_USR EQU 0x10 Startup.s(4): error: A1163E: Unknown opcode Mode_FIQ , expecting opcode or Macro Startup.s: 4 00000000 Mode_FIQ EQU 0x11 it is showing this same error till line 20 Startup.s(30): error: A1167E: Invalid line start like this it is showing me 51 errors but now if i remove the white spaces for first 20 lines it comes to two errors.....wat i have done is here
Mode_USR EQU 0x10 Mode_FIQ EQU 0x11 Mode_IRQ EQU 0x12 Mode_SVC EQU 0x13 Mode_ABT EQU 0x17 Mode_UND EQU 0x1B Mode_SYS EQU 0x1F
now it show 2 errors
Startup.s(21): error: A1163E: Unknown opcode STACK, , expecting opcode or Macro Startup.s(22): error: A1355U: A Label was found which was in no AREA
i have read the ARM Compiler toolchain Errors and Warnings Reference in it this error are A1163E
Unknown opcode <name> , expecting opcode or Macro
The most common reasons for this are:
Forgetting to put some white space on the left hand side margin, before the instruction, for example change:
MOV PC,LR
to
MOV PC,LR A1355U
A Label was found which was in no AREA
Example:
This can occur where no white-space precedes an assembler directive.
Assembler directives must be indented with white-space, for example use:
IF :DEF: FOO ; code ENDIF
instead of:
Symbols in the left-hand column are assumed to be labels. i tried this with spaces without spaces also but its still giving me the same errors.... plz help me with this