Hello Sir,
I am using LPC2368 timer2 for 10 us periodic interrupt. I am facing two problem 1 CPU is running at 60 Mhz then according to following setting of PCLKSEL0 and PCLKSEL1 all peripheral should be running at 60 Mhz. in order to get 10 us periodic interrupt I have to run timer at 1 us so T2PR value should be T2PR = 0x0000003B; but it works fine when T2PR = 0x0000000E;
PCONP = 0x00C0120E; PCLKSEL0 = 0x01000055; PCLKSEL1 = 0x00005000; void init_timer2(void) { T2PR = 0x0000003B; T2MR0 = 10; T2MCR = 3; T2TCR = 1; VICVectAddr26 = (unsigned long)tc2; VICIntEnable |= 1<<26; return; }
Second problem is that when code size of ISR routine size increases timer interrupt stops.
What,s the reason for that?
Thanks & Regards Rohit
I prefer code that have a tiny bit more comments than your code.
Note that not any facts can be read out from the source code - everything have to be extracted by going all the way to the user manual for the processor. That is a maintainance nightmare in the long run.
So you have 60 MHz CCLK.
Your PCLKSEL1 = 0x00005000 means that timer 2 have the 2 configuration bits 01 which would correspond to PCLK_TIMER2 = CCLK.
However, your actual results seems to indicate that PCLK for timer2 is CCLK/4. Or that your CCLK is 15 MHz.
Have you verified, that you _really_ do set up PCLKSEL1 as you say, because your results seems to match the factory default of CCLK/4?
Have you also verified that the processor itself really do have a CCLK of 60 MHz, and not 15 MHz?
Another thing - you say a value of 0x0000003B (=60-1) doesn't give the expected result, while 0x0000000E (16-1) does. If you had a division-by-4 error, I would have expected 0x0000000D (15-1) would have given the 1us tick rate of the timer (60/4)-1.
But then again - if you have the timer ticking at 1MHz (1us) then you shouldn't set the match register T2MR0 as 10 but as (10-1) to get a 10us period. A match register value of 10 would make the timer count 0, 1, 2, ... 9, 10, 0, 1, 2, ...
Second problem? Not sure. You have to start by posting your ISR. But at 10us with the processor at 60MHz, you have 600 clock cycles.
Yet another thing. You write "according to following setting of PCLKSEL0 and PCLKSEL1 all peripheral should be running at 60 Mhz". Why that claim? The bit values you have in PCLKSEL0 and PCLKSEL1 most definitely would not have all peripherials run at PCLK=CCLK. Maybe you mean "the peripherials I use". But that is something completely different from your claim. Look at UART1 for example - it has the clock bits as 00 which means CCLK/4.