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Hello guys, this is (maybe) not exactly Keil specific but I'm trying here anyway ;) I have an application using Keil RTX running on a LPC1778.
My os_idle_demon() in RTX_Conf_CM.c looks like this:
__task void os_idle_demon (void) { /* The idle demon is a system task, running when no other task is ready */ /* to run. The 'os_xxx' function calls are not allowed from this task. */ int x; for (;;) { // Only enable sleep if not running in debugger if ((CoreDebug->DHCSR & 0x0001)==0) { LPC_SC->PCON = 0x00; SCB->SCR = 0x00; __WFI(); } } }
Basically this will put the CPU in Sleep when no task is ready to run. Works perfect.
I then added a call to CLKPWR_PowerDown() in a function (when a button is pressed). The CLKPWR_PowerDown() funtion looks like this:
/*********************************************************************//** * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. * @param[in] None * @return None **********************************************************************/ void CLKPWR_PowerDown(void) { /* Deep-Sleep Mode, set SLEEPDEEP bit */ SCB->SCR = 0x4; LPC_SC->PCON = 0x09; /* Power Down Mode*/ __WFI(); }
This function also works as supposed.
BUT!
If I activate the deepsleep mode, the CPU will correctly go to deepsleep and wake up when an enabled interrupt fires (another GPIO pin). Only one problem, when waking up the CPU resets itself! This ONLY occurs if I have the Sleep code enabled in the os_idle_demon() ! I I disable the sleep code in the os_idle_demon() and enable it maybe 10 seconds later (using another button) it will reset immediatly!
So, Sleep on it's own works, deepsleep on it's own work, but when doing deepsleep followed by sleep the CPU resets. The other way around it is ok, the system can run forever just using the sleep in the os_idle_demon() and it also works when activating deepsleep. It is only when exiting from deepsleep and then doing sleep at some point in time in os_idle_demon() that the system resets.....
Any ideas out there before I loose the rest of my hair ?
Hi Per, thanks for the suggestion! I tried to grab the RSID (reset indentification register), and strange things happen :)
If I include the sleep and deepsleep in the program the device resets when awaken from the deepsleep as before. When I dump the RSID it shows 0x18 (BODR and SYSRESET) ! The brownout detect gives no sense as well as the sysreset. The SYSRESETREQ is not set by the program, and the brownout detect...I have no idea why that should be triggered by executing the sleep ?? Remember the I can extend the time to when the sleep is executed and as long as I extend the time to the sleep is executed the systems runs normally!
To be totally sure I will ofcourse measure the VddReg 3V3, just need a magnifying glass to find it (0201 and BGA components used all over :D) I'll be back with this, but I would be very surprized if that is not stable, after all why would that get unstable because of the sleep ? (if I just use the deepsleep all runs perfect when IRQ occurs and the device wakes up, only when the sleep is executed this error shows)
Update, just measured the RegVDD and sure enough, it is rock stable all the time (scope used etc) So why the device reports "brown out" is beyond me..... ???
Make sure that you clear the register after you have originally read it - when the processor resets it will not clear the register but add more bits to it.
So the brownout bit might be from the initial startup and need not have anything with that unexpected reset to do.
Hi Per, yes, already included in the code (RSID is set to 0x3F after the read of it). I have tested the various reset scenarios and I am able to detect and identify them all correctly so I'm sure that it is correct what I see in the case of the error.
You might have to send a mail to a NXP support engineer to ask about limitations of the sleep functions - and please update this thread with the outcome of such a query.
Note that the processor has an internal DC-DC since the core isn't running at 3V3. So maybe there are issues/limitations with the internal startup sequence of the processor after the deep sleep. I think at least some of the NXP chips can only reset after a deep sleep because they have powered off so much internal functionality that the processor can't restore all required state to allow the processor to just wake up and continue.
But any limitations should be documented in the latest processor user manual, or the latest errata.
Per, I have made a request to NXP also, I will write the outcome here also.
As I wrote I can delay the sleep 10 minutes after the device has been woken up from the deepsleep and it still happens, as soon as the sleep is invoked the CPU resets with the BOD reset and SYSRESETREQ flags set in RSID), the device starts immediatly from deepsleep when the interrupt occurs and the first thing I do is to initialize the PLLs and the clock divisors (as per the users manual).