Hello everybody.
I'm working on a Keil MCB4300 board with a LPC4357, and I've encounter a problem with the GPIO frequency. My program use two timers with interrupt to set and clear two GPIO, but the shortest time between the set and the clear is 120 ns (8,3 MHz). I use the PLL1 at 204 MHz for all the base clocks, so I would like to know if and how I can reduce the time min between the set and the clear.
This chip's GPIO itself should be fast enough. Did you consider the overhead of interrupts? According to your numbers, you have 24 cycles between set and clear. I doubt that you can improve on that with interrupts. Why do you have to use them?
I wasn't specific sorry, 120 ns is the time without interrupts, with interrupts the time is 1 µs. I use interrupts to synchronise with another board, timers create delay and lenght of an acquisition.
Note that the timer modules can normally be configured to automagically toggle specific processor pins, removing the jitter time of entering an interrupt handler.
Ok but I'm doing other instructions during the timer's interrupt routine, for example load and start the other timer, or change a variable to know if a acquisition is in progress.
So - the conclusion is that you don't have any issues with the speed of the GPIO pins.
But you might expect too much of the processor when it comes to quickly handle interrupts.
I try to gain time where I can, and with the GPIO commutating at 8 MHz with a core at 204 MHz, I think they could go faster.
Note that most NXP ARM chips have a configurable peripherial clock setting even for the GPIO.
I "manually" blit huge LED panels using the GPIO.
The base clock use for the GPIO is using the PLL (204 MHz), the PLL frequency and the configuration register for the GPIO clock are both correct.
The _full_ PLL, or a divided value from the PLL?
Because the PCLK normally defaults to be a fraction of the PLL output frequency. And when the core runs fast, then the GPIO hardware can only cache maybe two writes before it is forced to stall the core to get the GPIO subsystem to keep up.
It's using the full PLL, for the source clock you can choose the PLL or different clock divided from the PLL, and I choose the PLL.