I am using 8051F120 having 127KB Program memory, theoretically. I have written 4 *.C files residing in each bank. The length of the code in Bank1 and Bank2 is less than 32KB (observing the list file). But, instead of this, the linker gives an address space overflow for both the banks. Kindly assist.
Dhaval Solanki
why?
Because we live in the real world.
Even SiLabs - that bastion of high-end 8051 - now has ARM Cottex-M3 chips available...
I am sure someone will make Cottex-M3 chips sometime in the future but I doubt such a chip is available from anyone now, particularly Silabs.
Maybe a competitor for the Petnium?
But this is a discussion forum - not the Real World...
That sounds more likely, :)
More precisely, this is a discussion forum for real people talking about issues in the real world.
If you wish to talk about fantasy, I am sure there are other places for that where Keil products are not involved (I hope).
And would you like to say how much time do you spend on forums?
Nah, probably best if you don't.
Wooohoo hooooo.......guys wait. Please Relax and chill. Dear Andrew and Reluctant Consultant, I think we got diverted from the main topic.
To Andrew and Reluctant Consultant, I have knowledge on Cortex-M3 and Cortex-M3 is used for all the new project development. This is a back dated project, on which a lot of development has been done. And changing the platform now would consume a lot of time as well as cost. Hence, my project manager will be negative on changing of platform. Never the less, I would also, as my personal opinion, always work with latest controllers and technology. But, that's not in my hand. I'll have to get a break through on the existing problem.
Coming back to our issue.... Dear Dejan Durdenic, I have already read that datasheet (don't mean to sound rude or arrogant). Hence will you kindly highlight the exact paragraph, that gives the solution to my problem. I have read a lot of material on net, blogs and PDF's (For past 2 days, I am doing that).
Below are the details:
******** File1.lst file extracts *********** ******** Common Bank *********** MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 21521 ---- CONSTANT SIZE = 2318 ---- XDATA SIZE = 165 38 PDATA SIZE = ---- ---- DATA SIZE = ---- ---- C51 COMPILER V8.06 COMMON 04/28/2012 12:10:22 PAGE 72
IDATA SIZE = ---- ---- BIT SIZE = 5 ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
******** File2.lst file extracts *********** ******** Bank 1 *********** MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 32745 ---- CONSTANT SIZE = 1850 ---- XDATA SIZE = 2469 34 PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = 122 ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
******** File3.lst file extracts *********** ******** Bank 2 *********** MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 34208 ---- **refer the NOTE1 below. CONSTANT SIZE = 3569 ---- XDATA SIZE = 34 7 PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = 1 ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
******** File3.lst file extracts ********* ******** Bank 3 ********** MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 2316 ---- CONSTANT SIZE = 5952 ---- XDATA SIZE = 164 ---- PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
NOTE1: I know that the file size (in BANK2) is greater than 32KB, but than the linker should not show address space overflow in 'BANK1'. *** ERROR L107: ADDRESS SPACE OVERFLOW SPACE: BANK1
*** ERROR L107: ADDRESS SPACE OVERFLOW SPACE: BANK2
Below are the extracts of M51 file: TYPE BASE LENGTH RELOCATION SEGMENT NAME * * * * * * * C O D E B A N K 1 * * * * * * * 0000H 9881H *** GAP *** NOTE2 BANK1 9881H 1D5BH UNIT BANK1 B5DCH 1756H UNIT BANK1 CD32H 0D51H UNIT BANK1 DA83H 0623H UNIT BANK1 E0A6H 05DDH UNIT BANK1 E683H 0541H UNIT BANK1 EBC4H 044EH UNIT BANK1 F012H 03D7H UNIT BANK1 F3E9H 03BCH UNIT BANK1 F7A5H 033AH UNIT BANK1 FADFH 0322H UNIT BANK1 FE01H 01B4H UNIT BANK1 FFB5H 004BH UNIT
* * * * * * * C O D E B A N K 2 * * * * * * * 0000H 9881H *** GAP *** NOTE2 BANK2 9881H 03CCH UNIT BANK2 9C4DH 02A7H UNIT BANK2 9EF4H 02A7H UNIT BANK2 A19BH 0205H UNIT BANK2 A3A0H 0175H UNIT BL51 BANKED LINKER/LOCATER V6.05 04/30/2012 09:54:32 PAGE 5
BANK2 A515H 00F6H UNIT BANK2 A60BH 00B2H UNIT BANK2 A6BDH 0079H UNIT BANK2 A736H 0053H UNIT
* * * * * * * C O D E B A N K 3 * * * * * * * 0000H 9881H *** GAP *** NOTE2 BANK3 9881H 06ECH UNIT BANK3 9F6DH 0220H UNIT
NOTE2: Why does Bank start from 9981H and not from 8000H as stated in the datasheets? Prior to latest compilation, the starting address was A185H. And during that compilation,
the size of code overflowing + starting address = bank size
I fail to understand, why the starting address is not '8000H' as it should be? Kindly assist.
Dhaval
******** File1.lst file extracts *********** ******** Common Bank *********** MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 21521 ---- CONSTANT SIZE = 2318 ---- XDATA SIZE = 165 38 PDATA SIZE = ---- ---- DATA SIZE = ---- ---- C51 COMPILER V8.06 COMMON 04/28/2012 12:10:22 PAGE 72 IDATA SIZE = ---- ---- BIT SIZE = 5 ---- END OF MODULE INFORMATION. ******** File2.lst file extracts *********** ******** Bank 1 *********** MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 32745 ---- CONSTANT SIZE = 1850 ---- XDATA SIZE = 2469 34 PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = 122 ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) ******** File3.lst file extracts *********** ******** Bank 2 *********** MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 34208 ---- CONSTANT SIZE = 3569 ---- XDATA SIZE = 34 7 PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = 1 ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) ******** File3.lst file extracts ********* ******** Bank 3 ********** MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 2316 ---- CONSTANT SIZE = 5952 ---- XDATA SIZE = 164 ---- PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) NOTE1: I know that the file size (in BANK2) is greater than 32KB, but than the linker should not show address space overflow in 'BANK1'. *** ERROR L107: ADDRESS SPACE OVERFLOW SPACE: BANK1 *** ERROR L107: ADDRESS SPACE OVERFLOW SPACE: BANK2 Below are the extracts of M51 file: TYPE BASE LENGTH RELOCATION SEGMENT NAME * * * * * * * C O D E B A N K 1 * * * * * * * 0000H 9881H *** GAP *** NOTE2 BANK1 9881H 1D5BH UNIT BANK1 B5DCH 1756H UNIT BANK1 CD32H 0D51H UNIT BANK1 DA83H 0623H UNIT BANK1 E0A6H 05DDH UNIT BANK1 E683H 0541H UNIT BANK1 EBC4H 044EH UNIT BANK1 F012H 03D7H UNIT BANK1 F3E9H 03BCH UNIT BANK1 F7A5H 033AH UNIT BANK1 FADFH 0322H UNIT BANK1 FE01H 01B4H UNIT BANK1 FFB5H 004BH UNIT * * * * * * * C O D E B A N K 2 * * * * * * * 0000H 9881H *** GAP *** NOTE2 BANK2 9881H 03CCH UNIT BANK2 9C4DH 02A7H UNIT BANK2 9EF4H 02A7H UNIT BANK2 A19BH 0205H UNIT BANK2 A3A0H 0175H UNIT BL51 BANKED LINKER/LOCATER V6.05 04/30/2012 09:54:32 PAGE 5 BANK2 A515H 00F6H UNIT BANK2 A60BH 00B2H UNIT BANK2 A6BDH 0079H UNIT BANK2 A736H 0053H UNIT * * * * * * * C O D E B A N K 3 * * * * * * * 0000H 9881H *** GAP *** BANK3 9881H 06ECH UNIT BANK3 9F6DH 0220H UNIT NOTE2: Why does Bank start from 9981H and not from 8000H as stated in the datasheets? Prior to latest compilation, the starting address was A185H. And during that compilation, the size of code overflowing + starting address = bank size
You talk about information 'as stated in the datasheets'. I don't follow that part. The linker does not know (or read) the datasheets so it has to rely on what is provided to it.
Though quite interesting, the result of the linkage is probably not the best information to provide.
What I think would be more useful is the detail relating to the information provided to the linker.
Depending upon your listing settings, this information can be given at the start of the map file.
What you need to look at are the specifications relating to the common and the banked areas.
To Reluctant Consultant. 1. What I think would be more useful is the detail relating to the information provided to the linker. Are you referring to the following information:
Tool Chain Integration (window in SiLabs) Tool Vendor: Keil Assembler Tab: Command Line Flags: XR GEN DB EP NOMOD51. Compiler Tab: Command Line Flags: DB OE BR OR OT(8,Size) Large. Linker Tab: Command Line Flags: RS(256) PL(68) PW(78) BANKAREA(8000H,0FFFFH).
2. What you need to look at are the specifications relating to the common and the banked areas. Kindly elaborate, what I need to look at. I mean to say, I didn't exactly understand this line.
The datasheet specifications:
Common Bank Area: 0000H to 8000H Bank1 Area: 8000H to FFFFH Bank2 Area: 8000H to FFFFH Bank3 Area: 8000H to F7FFH
1KB of Address reserved in Bank3 (F800H to FFFFH).
The tool chain information is better, but I think that the information in the map file would be the most certain way of looking at the settings.
For example, in an old project of mine, the map file produced by the linker has a block of text that starts:
BL51 BANKED LINKER/LOCATER V5.03, INVOKED BY: C:\KEIL\C51\BIN\BL51.EXE BANK1 {.....etc.......}
The link settings used at time of the linker invokation should show what details are being specified for the common and banking details.
We can see from your details:
BANKAREA(8000H,0FFFFH)
So, the simplistic view would be that your banked code should start at 0x8000, but you need to check other parameters that might cause it to be starting further up.
Keil Compiler Options: Under Listing: Marked Check boxes: 1. Generate .lst file 2. Include Conditional code Warnings: Level 2 Optimization Level: Level 10 [Rearrange Code (Linker Optimization)] Emphasis Favor Small Code Memory Model: Variable Location: Large: XDATA Code Size Limits: 64K Functions Keil Linker Options: Under Linking: Marked Check boxes: 1. Enable Variable Overlaying RAM Size: 256 Selected Processor: C8051F120
Set the option to produce a linker map file, enable everything, do a rebuild (if necessary) and look for the information at the start that begins with something like:
The following extract from M51:
BL51 BANKED LINKER/LOCATER V6.05, INVOKED BY: C:\KEIL\C51\BIN\BL51.EXE D:\dhaval's disso\DissoVer4.41C_i2c\common.obj, D:\dhaval's disso\DissoVer4.41C_i2c\L51_BANK.obj, BANK1 {D:\dhaval's disso\DissoVer4.41C_i2c\main.obj}, BANK3 {D:\dhaval's disso\DissoVer4.41C_i2c\screens.obj}, D:\dhaval's disso\DissoVer4.41C_i2c\STARTUP.obj, BANK2 {D:\dhaval's disso\DissoVer4.41C_i2c\menu.obj} TO D:\dhaval's disso\DissoVer4.41C_i2c\TDT08L RS (256) PL (68) PW (78) BANKAREA (8000H, 0FFFFH)
What type of Parameters are you referring to? Can you give an example?
No. That's why you need to look at the settings carefully. There's obviously something missing or incorrect, otherwise it would be producing the output you expect.
I think you need to examine details relating to the 'common area'. I suspect the common code might be being placed at the start of each bank.
You mention that the datasheet specifies:
But, there is no specification of the common area in the linker invocation.
For example, my old project (which seems to have similarities to your memory layout) has a linker invocation containing:
BANKAREA (0X8000, 0XFFEF) RAMSIZE (256) DISABLEWARNING (16) CODE (0X0000-0X7FFF) XDATA (0X0000-0XFFFF)
Note the 'code' which I did not see in your linker invocation.
Just a hint - C51 linker does not show composite CODE+CONSTANT size. So, your BANK1 module takes 32745 bytes of CODE + 1850 bytes of CONSTANT space which together gives more than 32768 bytes. Try to solve BANK1 and BANK2 sizes first...
- Dejan