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I2C-Master in RTX

Hello!
I try to get the I2C2-Interface of my LPC2362 to work in RTX. I already got it work without RTX, where I oriented on sample code.
When I try the I2C2-Interface with the RTX, I observe that I cannot start the I2C-Communication (timeout). I assume that I do not get the interrupts from the I2C-Interface correctly (correct me if I am wrong).
Is there some special initialisation necessary, when using Interrupts in RTX? I configured the following, and I have no adaption in rtx_config.c...

VICVectAddr30 = (U32)I2C2MasterHandler; /* pointer for ISR */
VICVectCntl30 = 30; /* use it for I2C2 Interrupt */
VICIntEnable = (1 << 30); /* Enable Interrupt */

I apreciate any help.
Thanks a lot in advance!
Stefan

Parents
  • www.arm.com/.../cortex-m3_programming_for_arm7_developers.pdf

    For the ARM7TDMI processor, it is common for the interrupt handling to be implemented with an assembly code wrapper. This is required for nested interrupt handling, and for redirecting of interrupt requests to various interrupt handlers due to the IRQ vector being shared between all interrupts except FIQ (Fast Interrupt). This type of code wrapper can be completely eliminated on the Cortex-M3 processor because the exception mechanism automatically handles nested interrupts and executes the correct interrupt handler.

    Cortex-M3 processor exception handlers can be programmed as a C function with the saving and restoring of registers R0-R3, R12, R13, PSR and PC being carried out by the processor as part of its exception entry and return sequence.

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  • www.arm.com/.../cortex-m3_programming_for_arm7_developers.pdf

    For the ARM7TDMI processor, it is common for the interrupt handling to be implemented with an assembly code wrapper. This is required for nested interrupt handling, and for redirecting of interrupt requests to various interrupt handlers due to the IRQ vector being shared between all interrupts except FIQ (Fast Interrupt). This type of code wrapper can be completely eliminated on the Cortex-M3 processor because the exception mechanism automatically handles nested interrupts and executes the correct interrupt handler.

    Cortex-M3 processor exception handlers can be programmed as a C function with the saving and restoring of registers R0-R3, R12, R13, PSR and PC being carried out by the processor as part of its exception entry and return sequence.

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