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FlashFS / NAND - finit() returns 2

Mike Page

Hi all,

I'm trying to get a proof-of-concept FlashFS implementation on the Embedded Artists LPC2478 OEM board (using my own baseboard). The project is quite advanced and basic things like memory configuration can probably be considered working.

I have managed to get a RAM disk working as far as running finit(), fformat() and ffree() without problems. I'm using the NAND_LPC24xx.c driver and have set up File_Config.c for the device (K9F1G) also enabling software ECC. For now I am linking retarget.c but without STDIO, though I don't suspect that has any bearing on this particular issue. But I just get finit() returning 2, and if I ignore this error it locks up somewhere in fformat().

Having searched this forum a little, I have also implemented some just-in-case benign mods:
* Set up heap (8K).
* Make sure Ethernet and USB peripherals are powered.
* I am not using Microlib.

I am using v4.23 MDK Pro.

I guess my first question is does anyone have previous experience of FlashFS / NAND / EA LPC2478 OEM and can they offer any help? If not, does anyone have any hints?

Many thanks,
Mike Page.

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    For the benefit of any poor souls out there googling for answers!!

    I have been working with Keil on this one and it has come down to chip timing, specifically the following lines in NAND_LPC24xx.c, the Init() function:

    /* Delays are configured for CPU clock 72 MHz and low performance */
    EMC_STA_CFG (NAND0_HW_CS) = (1 << 7); /* BLSn[3:0] are Low for Read/Write */
    EMC_STA_WAITWEN (NAND0_HW_CS) = 4; /* Set Write Enable Delay (delay from CS to WE)*/
    EMC_STA_WAITOEN (NAND0_HW_CS) = 4; /* Set Output Enable Delay (delay from CS or addr change to OE*/
    EMC_STA_WAITRD (NAND0_HW_CS) = 6; /* Set Read Delay (delay from CS to read access) */
    EMC_STA_WAITPAGE(NAND0_HW_CS) = 4; /* Set Page Mode Read Delay */
    EMC_STA_WAITWR (NAND0_HW_CS) = 6; /* Set Write Delay (delay from CS to write access */
    EMC_STA_WAITTURN(NAND0_HW_CS) = 4; /* Set Turn Round Delay */

    With this I am able to get proof of concept, still working on integrating into my application.

    I have found that a heap of 0x800 is necessary.

    I will post an update when I have more concrete info.

    Mike.

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  • 0

    For the benefit of any poor souls out there googling for answers!!

    I have been working with Keil on this one and it has come down to chip timing, specifically the following lines in NAND_LPC24xx.c, the Init() function:

    /* Delays are configured for CPU clock 72 MHz and low performance */
    EMC_STA_CFG (NAND0_HW_CS) = (1 << 7); /* BLSn[3:0] are Low for Read/Write */
    EMC_STA_WAITWEN (NAND0_HW_CS) = 4; /* Set Write Enable Delay (delay from CS to WE)*/
    EMC_STA_WAITOEN (NAND0_HW_CS) = 4; /* Set Output Enable Delay (delay from CS or addr change to OE*/
    EMC_STA_WAITRD (NAND0_HW_CS) = 6; /* Set Read Delay (delay from CS to read access) */
    EMC_STA_WAITPAGE(NAND0_HW_CS) = 4; /* Set Page Mode Read Delay */
    EMC_STA_WAITWR (NAND0_HW_CS) = 6; /* Set Write Delay (delay from CS to write access */
    EMC_STA_WAITTURN(NAND0_HW_CS) = 4; /* Set Turn Round Delay */

    With this I am able to get proof of concept, still working on integrating into my application.

    I have found that a heap of 0x800 is necessary.

    I will post an update when I have more concrete info.

    Mike.

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