Hi,
In the following driver code (In Keil MDK4: .../Keil/ARM/RL/TCPNet/Drivers/STR9_ENET.c), It says that "Configure VIC for EMAC interrupt" and it uses "14" as index of VIC->VAiR[14] for EMAC, however In datasheet of STR912FAxx www.st.com/.../CD00159308.pdf it says VIC0.11 Ethernet MAC Logic OR of Ethernet MAC interrupts via its own dedicated DMA channel on page 19.
STR9_ENET.c file is suitable for STR912FAW44(on Keil's MCBSTR9) devices?
VIC0->DVAR = (U32)def_interrupt; VIC0->VAiR[14] = (U32)interrupt_ethernet; VIC0->INTSR &= ~(1 << 11); VIC0->VCiR[14] = 0x20 | 11;
/*---------------------------------------------------------------------------- * RL-ARM - TCPnet *---------------------------------------------------------------------------- * Name: STR9_ENET.C * Purpose: Driver for ST STR912 ENET Ethernet Controller * Rev.: V4.20 *---------------------------------------------------------------------------- * This code is part of the RealView Run-Time Library. * Copyright (c) 2004-2011 KEIL - An ARM Company. All rights reserved. *---------------------------------------------------------------------------*/ #include <Net_Config.h> #include "STR9_ENET.h" #include <91x_lib.h> /* STR912F definitions */ .... void init_ethernet (void) { /* Initialize the ENET ethernet controller. */ U32 regv,tout,id1,id2; /* Reset ENET and DMA devices. */ ENET_DMA->SCR |= SCR_SRESET; /* Enable GPIO1 Ethernet Pins. */ GPIO1->DDR |= 0x9E; GPIO1->DR[0x9E<<2] = 0x00; SCU->GPIOTYPE[1] &= ~0x9E; SCU->GPIOIN[1] &= ~0x9E; SCU->GPIOOUT[1] &= ~0xC3FC; SCU->GPIOOUT[1] |= 0x82A8; /* Enable GPIO5 Ethernet Pins, drive MII clock 25MHz. */ GPIO5->DDR |= 0x0C; GPIO5->DR[0x0C<<2] = 0x00; SCU->GPIOTYPE[5] &= ~0x0C; SCU->GPIOIN[5] &= ~0x0C; SCU->GPIOOUT[5] &= ~0x00F0; SCU->GPIOOUT[5] |= 0x00A0; /* Remove reset for ENET and MAC devices */ ENET_DMA->SCR &= ~SCR_SRESET; /* Initialize MAC control register, accept multicast packets. */ ENET_MAC->MCR = MCR_PFM_MCAST | MCR_RVFF | MCR_APR | MCR_DCE; /* If HCLK > 50MHz enable the following line. */ //ENET_MAC->MCR |= MCR_PS_DEF; /* Setup Tx & Rx burst size. */ regv = ENET_DMA->SCR & ~(SCR_TX_BURST_SIZE | SCR_RX_BURST_SIZE); ENET_DMA->SCR = regv | (SCR_TX_BURST_DEF | SCR_RX_BURST_DEF); /* Set clock to PCLK */ ENET_DMA->CCR = (ENET_DMA->CCR & CCR_SEL_CLK) | CCR_SEL_CLK_DEF; /* Put the STE100P in reset mode */ write_PHY (PHY_REG_XCR, 0x8000); /* Wait for hardware reset to end. */ for (tout = 0; tout < 0x100000; tout++) { regv = read_PHY (PHY_REG_XCR); if (!(regv & 0x8000)) { /* Reset complete */ break; } } /* Check if this is a STE100P PHY. */ id1 = read_PHY (PHY_REG_PID1); id2 = read_PHY (PHY_REG_PID2); if (((id1 << 16) | (id2 & 0xFFF0)) == STE100P_ID) { /* Configure the PHY device */ #if defined (_10MBIT_) /* Connect at 10MBit */ write_PHY (PHY_REG_XCR, PHY_FULLD_10M); #elif defined (_100MBIT_) /* Connect at 100MBit */ write_PHY (PHY_REG_XCR, PHY_FULLD_100M); #else /* Use autonegotiation about the link speed. */ write_PHY (PHY_REG_XCR, PHY_AUTO_NEG); /* Wait to complete Auto_Negotiation. */ for (tout = 0; tout < 0x100000; tout++) { regv = read_PHY (PHY_REG_XSR); if (regv & 0x0020) { /* ANEG_ACK set, autonegotiation finished. */ break; } } #endif } /* Check the link status. */ for (tout = 0; tout < 0x10000; tout++) { regv = read_PHY (PHY_REG_XSR); if (regv & 0x0004) { /* Link is on. */ break; } } regv = read_PHY (PHY_REG_XCIIS); if (regv & 0x0100) { /* Full duplex is enabled. */ ENET_MAC->MCR |= MCR_FDM; } else { /* Half duplex mode. */ ENET_MAC->MCR |= MCR_DRO; } /* Set the Ethernet MAC Address registers */ ENET_MAC->MAH = ((U32)own_hw_adr[5] << 8) | (U32)own_hw_adr[4]; ENET_MAC->MAL = ((U32)own_hw_adr[3] << 24) | ((U32)own_hw_adr[2] << 16) | ((U32)own_hw_adr[1] << 8) | (U32)own_hw_adr[0]; /* Initialize Tx and Rx DMA Descriptors */ rx_descr_init (); tx_descr_init (); /* Force a ENET abort by software */ ENET_DMA->RXSTR |= RXSTR_DMA_EN; ENET_DMA->TXSTR |= TXSTR_DMA_EN; /* Setup Descriptor Fetch Delay */ ENET_DMA->RXSTR = (ENET_DMA->RXSTR & ~RXSTR_DFETCH_DLY) | RXSTR_DFETCH_DEF | RXSTR_COLL_SEEN | RXSTR_RUNT_FRAME | RXSTR_FILTER_FAIL; ENET_DMA->TXSTR = (ENET_DMA->TXSTR & ~TXSTR_DFETCH_DLY) | TXSTR_DFETCH_DEF | TXSTR_UNDER_RUN; /* Enable ENET interrupts. */ ENET_DMA->IER = INT_RX_CURR_DONE | INT_TX_CURR_DONE | INT_RX_DONE; /* Reset all interrupts */ ENET_DMA->ISR = 0xFFFFFFFF; /* Enable receive and transmit mode of MAC Ethernet core */ ENET_MAC->MCR |= (MCR_TE | MCR_RE); /* Start the receive operation */ ENET_DMA->RXSTR |= RXSTR_START_FETCH; /* Configure VIC for EMAC interrupt. */ VIC0->DVAR = (U32)def_interrupt; VIC0->VAiR[14] = (U32)interrupt_ethernet; VIC0->INTSR &= ~(1 << 11); VIC0->VCiR[14] = 0x20 | 11; }