hi, i use software simulator of MDK 4.21 for LPC1114 GPIO. here is the Code:
int main (void) {
int i;
LPC_GPIO[0]->DIR |= (1<<1); //prot0.1 as output
LPC_GPIO[0]->DIR |= (1<<2); //port0.2 as output
while( 1 )
{
LPC_GPIO[0]->MASKED_ACCESS[1<<1] = (1<<1); //set port0.1 as 1
for(i=0;i<10000;i++);
LPC_GPIO[0]->MASKED_ACCESS[1<<2] = (0<<2); //set port0.2 as 0
}
When the first statement(set port0.1 as 1) finished, the simulator work OK, the port0.1 is 1. but when the next statement(set port0.2 as 0) finished, it clear the port0.2 as 0, and Port0.1 has been cleard to 0 also!!
The user manual - §9.2.1 - says: "Reading and writing of data registers are masked by address bits 13:2"
And §9.4.1 shows a diagram where two least significant bits of the mask address isn't used.
so 1<<2 is mask address for port0.0 and 1<<3 is mask address for port0.1 and 1<<4 is mask address for port0.2
Thank you, Per. I read the manual and noticed "Reading and writing of data registers are masked by address bits 13:2". My code include the file of MDK: <LPC11xx.h>. in this file, the IO-Port of LPC1114 is defined as below:
#define LPC_AHB_BASE (0x50000000UL) ...... #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) ...... #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) ...... typedef struct { union { __IO uint32_t MASKED_ACCESS[4096]; struct { uint32_t RESERVED0[4095]; __IO uint32_t DATA; }; }; uint32_t RESERVED1[4096]; __IO uint32_t DIR; __IO uint32_t IS; __IO uint32_t IBE; __IO uint32_t IEV; __IO uint32_t IE; __I uint32_t RIS; __I uint32_t MIS; __O uint32_t IC; } LPC_GPIO_TypeDef;
Please see the struct of LPC_GPIO_TypeDef, the MASKED_ACCESS is a array of uint32_t(4 BYTE). the address of LPC_GPIO0 is 0x50000000UL, so, when we set port0.0 as 1, wen can write: LPC_GPIO[0]->MASKED_ACCESS[1<<0] = (1<<0), 1<<0 is 1, the address of MASKED_ACCESS[1<<0] is 0x50000004; and if set port0.1 as 1, can write: LPC_GPIO[0]->MASKED_ACCESS[1<<1] = (1<<1), 1<<1 is 2, the address of MASKED_ACCESS[1<<1] is 0x50000008; These options is done with the same effect as "Reading and writing of data registers are masked by address bits 13:2". address left shift 2 bit is as same as increase with 4 Byte.
Infact, I try a similar code on my hardware board, it work correctly.
Hi
I am running V4.50 and am also seeing behavior which doesn't agree with my understanding of the documentation when using the Simulator with GPIO. According to the NXP document UM10398, page 115 the GPIODATA register address is ANDed with actual data written to mask the writing of the information through to the output pins. As such if i write:
LPC_GPIO2->MASKED_ACCESS[1 << 5] = 0xfff;
i should just see bit 5 of the output go active BUT i see ALL the pins go active!
This also follows for clearing them, writing a 0 writes through to ALL the bits.
Does anybody else agree with my observations?
I have noticed that a lot of code examples use the following code:
LPC_GPIO2->MASKED_ACCESS[1 << 5] = 1 << 5; // set LPC_GPIO2->MASKED_ACCESS[1 << 5] = ~(1 << 5); // clear
so i was wondering if the simulator IS correct (well it agrees with the hardware) and the documentation is wrong? I have used the Luminary Micro part which behaves in a very similar fashion but only 8 bits and that seems to work fine.
I currently don't have any access to hardware to test this on so have been relying on the simulator.
Thanks for any help that people have had.