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I have two question on SSP1 of LPC1768
1. We have configured SSP1 as TI SSI for receiving 16 bits of data. We have connected Sclk pin to Clock of salve and MISO pin to Data pin of Slave.We have generated clock to receive data from our slave. If i send the clock then SPDR value is getting updated but RNE bit is not set thus we are not able to read SPDr value. If we send the clock again my SPDR is always 0.
2. Can we read 18 bit data from the SSP1 which is configured as TI SSI with DSS as 9 bit and receiving SPDR value twice.
Code:
int main() { int j; SystemInit(); SSP1Init(); LPC_SSP1->DR=0x0000; SSPSend(1,0x0000,16); while(1) { } }
void SSP1Init( void ) { uint8_t i, Dummy=Dummy; LPC_SC->PCONP |= (0x1<<10);/* Enable AHB clock to the SSP1. */ LPC_SC->PCLKSEL0 &= ~(0x3<<20); /* P0.6~0.9 as SSP1 */ LPC_PINCON->PINSEL0 &= ~((0x3<<12)|(0x3<<16)|(0x3<<18)); LPC_PINCON->PINSEL0 |= ((0x2<<12)|(0x2<<16)|(0x2<<18)); /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */ LPC_SSP1->CR0 = 0x075F; /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */ LPC_SSP1->CPSR = 0x2; for ( i = 0; i < FIFOSIZE; i++ ) { Dummy = LPC_SSP1->DR; /* clear the RxFIFO */ } NVIC_EnableIRQ(SSP1_IRQn); /* Enable the SSP Interrupt */ LPC_SSP1->CR1 = SSPCR1_SSE;/* Master mode *//* Device select as master, SSP Enabled */ /* Set SSPINMS registers to enable interrupts */ /* enable all error related interrupts */ LPC_SSP1->IMSC = SSPIMSC_RORIM | SSPIMSC_RTIM; return; }
void SSPSend( uint32_t portnum, uint16_t buf) { uint32_t i; uint16_t Dummy = Dummy,receive[9]; if ( portnum == 1 ) { /* Move on only if NOT busy and TX FIFO not full. */ while ( (LPC_SSP1->SR & (SSPSR_TNF|SSPSR_BSY)) != SSPSR_TNF ); LPC_SSP1->DR = buf; //buf++; #if !LOOPBACK_MODE while ( (LPC_SSP1->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE ); LPC_SSP1->DR=0x0000; receive[0] = LPC_SSP1->DR; #else /* Wait until the Busy bit is cleared. */ while ( LPC_SSP1->SR & SSPSR_BSY ); #endif } return; }
It is TI SSI communication only. We have initialized SSP as SSI. Its wrongly commented. Our slave has only 2 lines CLK and DAT. If i send 16 pulses then i receive 16 bit of data. We are not using FS and MOSI pins of the SSP1 block. If a 16 bit data is sent SPDR value is getting updated with the received bytes but RNE flag is low.We are not able to read the data from shift register.
Sp is there a reason why you don't want your comments to match your code?
/* P0.6~0.9 as SSP1 */ LPC_PINCON->PINSEL0 &= ~((0x3<<12)|(0x3<<16)|(0x3<<18)); LPC_PINCON->PINSEL0 |= ((0x2<<12)|(0x2<<16)|(0x2<<18));
You claim 4 pins are configured, but the code only configures 3.
/* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
You claim 8-bit but configure 16-bit. You claim SPI but configure TI. You claim CPOL and CPHA but they aren't applicable for TI.
You show a call in main looking like:
SSPSend(1,0x0000,16);
while you show an actual implementation looking like:
void SSPSend( uint32_t portnum, uint16_t buf)
Three parameters sent, and two received...
So lots of noise that tells a different story in the code. That doesn't really help.
And you still haven't explained your code doing two writes and one read. How do you expect to get a balance between receive FIFO and transmit FIFO with such code? In reality, you have three sends, since you start with writing a word in main() before you even call your send function.
You only use two signals. How is your external device then expected to find any frame synchronization to know when it's time for the most significant bit?
And your original post talks about an 18-bit transfer. But the TI protocol uses FS once for each transfer, so if the device expects an 18-bit transfer then it expects one clock pulse with FS and then 18 clock pulses for the data. Potentially with the last clock pulse having FS active again to indicate the start of yet another word transfer directly after the last bit of the previous word transfer.