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I have two question on SSP1 of LPC1768
1. We have configured SSP1 as TI SSI for receiving 16 bits of data. We have connected Sclk pin to Clock of salve and MISO pin to Data pin of Slave.We have generated clock to receive data from our slave. If i send the clock then SPDR value is getting updated but RNE bit is not set thus we are not able to read SPDr value. If we send the clock again my SPDR is always 0.
2. Can we read 18 bit data from the SSP1 which is configured as TI SSI with DSS as 9 bit and receiving SPDR value twice.
Code:
int main() { int j; SystemInit(); SSP1Init(); LPC_SSP1->DR=0x0000; SSPSend(1,0x0000,16); while(1) { } }
void SSP1Init( void ) { uint8_t i, Dummy=Dummy; LPC_SC->PCONP |= (0x1<<10);/* Enable AHB clock to the SSP1. */ LPC_SC->PCLKSEL0 &= ~(0x3<<20); /* P0.6~0.9 as SSP1 */ LPC_PINCON->PINSEL0 &= ~((0x3<<12)|(0x3<<16)|(0x3<<18)); LPC_PINCON->PINSEL0 |= ((0x2<<12)|(0x2<<16)|(0x2<<18)); /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */ LPC_SSP1->CR0 = 0x075F; /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */ LPC_SSP1->CPSR = 0x2; for ( i = 0; i < FIFOSIZE; i++ ) { Dummy = LPC_SSP1->DR; /* clear the RxFIFO */ } NVIC_EnableIRQ(SSP1_IRQn); /* Enable the SSP Interrupt */ LPC_SSP1->CR1 = SSPCR1_SSE;/* Master mode *//* Device select as master, SSP Enabled */ /* Set SSPINMS registers to enable interrupts */ /* enable all error related interrupts */ LPC_SSP1->IMSC = SSPIMSC_RORIM | SSPIMSC_RTIM; return; }
void SSPSend( uint32_t portnum, uint16_t buf) { uint32_t i; uint16_t Dummy = Dummy,receive[9]; if ( portnum == 1 ) { /* Move on only if NOT busy and TX FIFO not full. */ while ( (LPC_SSP1->SR & (SSPSR_TNF|SSPSR_BSY)) != SSPSR_TNF ); LPC_SSP1->DR = buf; //buf++; #if !LOOPBACK_MODE while ( (LPC_SSP1->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE ); LPC_SSP1->DR=0x0000; receive[0] = LPC_SSP1->DR; #else /* Wait until the Busy bit is cleared. */ while ( LPC_SSP1->SR & SSPSR_BSY ); #endif } return; }
Yes, I do know you need to write to the controller to force the clock pulses that results in the required read. My note was that you describe the _read_ as a dummy operation, indicating that it is the _write_ that is the real operation performed.
You didn't mention anything about the lack of delay in your code - how you make sure that the monoflop resets before next transfer, since that is the synchronization needed by the sensor to make sure it starts with sending out MSB and not continue to send the two least significant bits before starting with the 16 most significant bits of next read.
"hence we tried reading the data at the falling edge by changing the CPHA."
How? I have already two times notified you to CPHA being an SPI setting - but you don't configure SPI. You configure the TI mode.
From the manual: CPOL: "Clock Out Polarity. This bit is only used in SPI mode." CPHA: "Clock Out Phase. This bit is only used in SPI mode."
So in this case, the SPI mode would map better to your actual needs than trying the TI mode, if you want the CPOL and CPHA bits to actually mean anything.
Of course, differential signals would normally solve polarity by you switching Clock+ and Clock- unless you have already shipped the hardware and cabling.