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How does uVision start executing M3 flash OS from RAM?

It seems the flash programming algorithm is a piece of code that is downloaded into the SRAM and executes from there.

But how does it get started if there is nothing yet in the vector table at 0? If the flash is erased then everything in the vector table at zero will be 0xFFFFFFFF, so how does it start executing the algorithm in RAM? (which is at 0x20000000 for example)

I want to know because I want to be able to boot from RAM as well.

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  • You can't reset your processor when debugging in RAM. Or more specifically: You can't reset it and expect it to be able to start your program a second time.

    You can have the debugger set the PC to the correct start address. And you can then have your own startup code configure the VTOR (I assume it stands for something like Vector Table Offset Register for your specific processor) to tell the core exactly where the interrupt vector table is.

    So as long as both code + data fits in your RAM, you can debug in RAM. But the debugger must be involved to fix an initial PC value if you try to reset the processor.

    Note that not all processors allows execution from all RAM memory ranges. Some RAM may be located on a separate memory bus intended for DMA transfers to/from peripherial hardware. The processor pipeline and any code cache needs integration with used RAM regions to make sure everything works as intended.

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  • You can't reset your processor when debugging in RAM. Or more specifically: You can't reset it and expect it to be able to start your program a second time.

    You can have the debugger set the PC to the correct start address. And you can then have your own startup code configure the VTOR (I assume it stands for something like Vector Table Offset Register for your specific processor) to tell the core exactly where the interrupt vector table is.

    So as long as both code + data fits in your RAM, you can debug in RAM. But the debugger must be involved to fix an initial PC value if you try to reset the processor.

    Note that not all processors allows execution from all RAM memory ranges. Some RAM may be located on a separate memory bus intended for DMA transfers to/from peripherial hardware. The processor pipeline and any code cache needs integration with used RAM regions to make sure everything works as intended.

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