It is said that 8051 has an on-chip oscillator but requires external clock to run it. What may be the internal circuit for on-chip oscillator, how it runs after connecting crystal oscillator? Also what is the purpose of external capacitor with crystal oscillator?
Many (most?) modern 8051 derivatives take less than 12 clocks per instruction.
Again, see the datasheet for the particular chip for specific details
The books say - "The 8051 has an on-chip clock generation circuit" and not 8051 has on-chip oscillator . The 8051 based architecture chips have on-chip clock generation circuit.
It simply means that there is a Mod-12 counter. The externally applied clock signal (which may be given from a function generator, crystal oscillator or RC oscillator, though crystal oscillator is preferred) will be divide by 12 and then applied to the CPU.
NO, NO!! the '51 has an internal oscillator that requires an external crystal to function. there is no requirement for "a function generator, crystal oscillator or RC oscillator". some modern derivatives can even run (while not as precisely clocked) without a crystal.
The traditional 8051 is very old, and made with a minimum of transistors. So one instruction is handled at a time, and the processor needs a large number of clock cycles to sequence all the "book keeping" for that single instruction. this is not true for most modern derivatives
Erik
"this is not true for most modern derivatives"
Which is why I started my post with the sentence "The 12-clock feature of the original 8051 isn't to remove any noise." (emphasis on "original" added now)
Today, transistors are almost free. With a design where the inner transistors are very small and just the I/O transistors are scaled large for protection and current drive capability, the transistors consumes very little space and requires very little power. So no longer a need for long sequence machines just to process a single instruction.
Smaller transistors also means less capacitance and shorter travel distance for the signals, so there are less need for wait states for data to travel around the chips.