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Debug LPC 1788

I have 2 projects:

bootloader project - mount the SD card and load application.hex to the external RAM
application project - RTOS and application

I would like to use bootload to load a application.hex(on SD card) to the external RAM and run. But how to debug the application?

Parents
  •         //*********************************************
        // DYNAMIC MEMORY CONFIGURATION
        //*********************************************
        _WDWORD(EMCDLYCTL_REG,      0x00000A05);                    //LPC_SC->EMCDLYCTL   = 0x00000A05;
    
        _WDWORD(EMC_CTRL_REG,   0x1);                               // LPC_EMC->Control = 0x00000001;
        _WDWORD(EMC_CONFIG_REG, 0x0);                               // LPC_EMC->Config  = 0x00000000;
    
        _WDWORD(SCS_REG,        _RDWORD(SCS_REG) |  (1<<1));        //LPC_SC->SCS |= (1<<1);
        _WDWORD(SCS_REG,        _RDWORD(SCS_REG) & ~(0x00000001));  //LPC_SC->SCS &= ~(0x00000001);
    
    
        _WDWORD(EMC_DYN_CFG0_REG,   0x00001680);    //LPC_EMC->DynamicConfig0 = 0x00001680;
        _WDWORD(EMCDLYCTL_REG,      0x00000A05);
    
        _WDWORD(EMC_DYN_RASCAS0_REG, 2 + (2<<8));   //LPC_EMC->DynamicRasCas0 = RAS_Latency + (CAS_Latency<<8);
    
        _WDWORD(EMC_DYN_RD_CFG_REG, 0x00000001);        //LPC_EMC->DynamicReadConfig = 0x00000001;
    
        _WDWORD(EMC_DYN_RP_REG,     NS_2_CLKS(18));     //LPC_EMC->DynamicRP   = NS_2_CLKS(18);
        _WDWORD(EMC_DYN_RAS_REG,    NS_2_CLKS(42));     //LPC_EMC->DynamicRAS  = NS_2_CLKS(42);
        _WDWORD(EMC_DYN_SREX_REG,   NS_2_CLKS(70));     //LPC_EMC->DynamicSREX = NS_2_CLKS(70);
        _WDWORD(EMC_DYN_APR_REG,    NS_2_CLKS(18));     //LPC_EMC->DynamicAPR  = NS_2_CLKS(18);
        _WDWORD(EMC_DYN_DAL_REG,    4);                 //LPC_EMC->DynamicDAL  = CAS_Latency+2;
        _WDWORD(EMC_DYN_WR_REG,     (NS_2_CLKS(6)+1));  //LPC_EMC->DynamicWR   = (NS_2_CLKS(6)+1);
        _WDWORD(EMC_DYN_RC_REG,     NS_2_CLKS(60));     //LPC_EMC->DynamicRC   = NS_2_CLKS(60);
        _WDWORD(EMC_DYN_RFC_REG,    NS_2_CLKS(60));     //LPC_EMC->DynamicRFC  = NS_2_CLKS(60);
        _WDWORD(EMC_DYN_XSR_REG,    NS_2_CLKS(70));     //LPC_EMC->DynamicXSR  = NS_2_CLKS(70);
        _WDWORD(EMC_DYN_RRD_REG,    NS_2_CLKS(12));     //LPC_EMC->DynamicRRD  = NS_2_CLKS(12);
        _WDWORD(EMC_DYN_MRD_REG,    2);                 //LPC_EMC->DynamicMRD  = 2;
    
        _WDWORD(EMC_DYN_CTRL_REG,   0x00000183);        //LPC_EMC->DynamicControl = 0x00000183;
    
        _sleep_(2);
    
        _WDWORD(EMC_DYN_CTRL_REG,   0x00000103);        //LPC_EMC->DynamicControl = 0x00000103;
        _WDWORD(EMC_DYN_RFSH_REG,   0x00000001);        //LPC_EMC->DynamicRefresh = 0x00000001;  // 1 x 16 = 16 CCLKs between SDRAM refresh cycles
    
        _sleep_(1);
    
        _WDWORD(EMC_DYN_RFSH_REG,   NS_2_CLKS(7813 + 1)>>4);  //LPC_EMC->DynamicRefresh = NS_2_CLKS(7813 + 1)>>4;     // Refresh units are x16 (8192 rows...)
    
        _sleep_(1);
    
        _WDWORD(EMC_DYN_CTRL_REG,   0x00000083);        //LPC_EMC->DynamicControl    = 0x00000083; /* Issue MODE command */
    
        _RDWORD(SDRAM_BASE_ADDR|((0x03+(2<<4))<<10));   //Temp = *((volatile uint32_t *)(SDRAM_BASE_ADDR|((0x03+(CAS_Latency<<4))<<10)));
    
        _sleep_(1);
    
        _WDWORD(EMC_DYN_CTRL_REG,    0x00000000);        //LPC_EMC->DynamicControl = 0x00000000;
        _WDWORD(EMC_DYN_CFG0_REG,    _RDWORD(EMC_DYN_CFG0_REG) | 0x00080000);    //LPC_EMC->DynamicConfig0 |= 0x00080000;
    
        //*********************************************
        // STATIC MEMORY CONFIGURATION
        //*********************************************
        _WDWORD(EMC_STA_CFG0_REG,   0x00000081);    // LPC_EMC->StaticConfig0   = 0x00000081;
        _WDWORD(EMC_STA_WWEN0_REG,  0x00000003);    // LPC_EMC->StaticWaitWen0  = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
        _WDWORD(EMC_STA_WOEN0_REG,  0x00000003);    // LPC_EMC->StaticWaitOen0  = 0x00000003; /* ( n     ) -> 0 clock cycles */
        _WDWORD(EMC_STA_WRD0_REG,   0x00000006);    // LPC_EMC->StaticWaitRd0   = 0x00000006; /* ( n + 1 ) -> 7 clock cycles */
        _WDWORD(EMC_STA_WPAGE0_REG, 0x00000003);    // LPC_EMC->StaticWaitPage0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
        _WDWORD(EMC_STA_WWR0_REG,   0x00000005);    // LPC_EMC->StaticWaitWr0   = 0x00000005; /* ( n + 2 ) -> 7 clock cycles */
        _WDWORD(EMC_STA_WTURN0_REG, 0x00000003);    // LPC_EMC->StaticWaitTurn0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
    }
    
    
    init_emc();
    Setup();
    

Reply
  •         //*********************************************
        // DYNAMIC MEMORY CONFIGURATION
        //*********************************************
        _WDWORD(EMCDLYCTL_REG,      0x00000A05);                    //LPC_SC->EMCDLYCTL   = 0x00000A05;
    
        _WDWORD(EMC_CTRL_REG,   0x1);                               // LPC_EMC->Control = 0x00000001;
        _WDWORD(EMC_CONFIG_REG, 0x0);                               // LPC_EMC->Config  = 0x00000000;
    
        _WDWORD(SCS_REG,        _RDWORD(SCS_REG) |  (1<<1));        //LPC_SC->SCS |= (1<<1);
        _WDWORD(SCS_REG,        _RDWORD(SCS_REG) & ~(0x00000001));  //LPC_SC->SCS &= ~(0x00000001);
    
    
        _WDWORD(EMC_DYN_CFG0_REG,   0x00001680);    //LPC_EMC->DynamicConfig0 = 0x00001680;
        _WDWORD(EMCDLYCTL_REG,      0x00000A05);
    
        _WDWORD(EMC_DYN_RASCAS0_REG, 2 + (2<<8));   //LPC_EMC->DynamicRasCas0 = RAS_Latency + (CAS_Latency<<8);
    
        _WDWORD(EMC_DYN_RD_CFG_REG, 0x00000001);        //LPC_EMC->DynamicReadConfig = 0x00000001;
    
        _WDWORD(EMC_DYN_RP_REG,     NS_2_CLKS(18));     //LPC_EMC->DynamicRP   = NS_2_CLKS(18);
        _WDWORD(EMC_DYN_RAS_REG,    NS_2_CLKS(42));     //LPC_EMC->DynamicRAS  = NS_2_CLKS(42);
        _WDWORD(EMC_DYN_SREX_REG,   NS_2_CLKS(70));     //LPC_EMC->DynamicSREX = NS_2_CLKS(70);
        _WDWORD(EMC_DYN_APR_REG,    NS_2_CLKS(18));     //LPC_EMC->DynamicAPR  = NS_2_CLKS(18);
        _WDWORD(EMC_DYN_DAL_REG,    4);                 //LPC_EMC->DynamicDAL  = CAS_Latency+2;
        _WDWORD(EMC_DYN_WR_REG,     (NS_2_CLKS(6)+1));  //LPC_EMC->DynamicWR   = (NS_2_CLKS(6)+1);
        _WDWORD(EMC_DYN_RC_REG,     NS_2_CLKS(60));     //LPC_EMC->DynamicRC   = NS_2_CLKS(60);
        _WDWORD(EMC_DYN_RFC_REG,    NS_2_CLKS(60));     //LPC_EMC->DynamicRFC  = NS_2_CLKS(60);
        _WDWORD(EMC_DYN_XSR_REG,    NS_2_CLKS(70));     //LPC_EMC->DynamicXSR  = NS_2_CLKS(70);
        _WDWORD(EMC_DYN_RRD_REG,    NS_2_CLKS(12));     //LPC_EMC->DynamicRRD  = NS_2_CLKS(12);
        _WDWORD(EMC_DYN_MRD_REG,    2);                 //LPC_EMC->DynamicMRD  = 2;
    
        _WDWORD(EMC_DYN_CTRL_REG,   0x00000183);        //LPC_EMC->DynamicControl = 0x00000183;
    
        _sleep_(2);
    
        _WDWORD(EMC_DYN_CTRL_REG,   0x00000103);        //LPC_EMC->DynamicControl = 0x00000103;
        _WDWORD(EMC_DYN_RFSH_REG,   0x00000001);        //LPC_EMC->DynamicRefresh = 0x00000001;  // 1 x 16 = 16 CCLKs between SDRAM refresh cycles
    
        _sleep_(1);
    
        _WDWORD(EMC_DYN_RFSH_REG,   NS_2_CLKS(7813 + 1)>>4);  //LPC_EMC->DynamicRefresh = NS_2_CLKS(7813 + 1)>>4;     // Refresh units are x16 (8192 rows...)
    
        _sleep_(1);
    
        _WDWORD(EMC_DYN_CTRL_REG,   0x00000083);        //LPC_EMC->DynamicControl    = 0x00000083; /* Issue MODE command */
    
        _RDWORD(SDRAM_BASE_ADDR|((0x03+(2<<4))<<10));   //Temp = *((volatile uint32_t *)(SDRAM_BASE_ADDR|((0x03+(CAS_Latency<<4))<<10)));
    
        _sleep_(1);
    
        _WDWORD(EMC_DYN_CTRL_REG,    0x00000000);        //LPC_EMC->DynamicControl = 0x00000000;
        _WDWORD(EMC_DYN_CFG0_REG,    _RDWORD(EMC_DYN_CFG0_REG) | 0x00080000);    //LPC_EMC->DynamicConfig0 |= 0x00080000;
    
        //*********************************************
        // STATIC MEMORY CONFIGURATION
        //*********************************************
        _WDWORD(EMC_STA_CFG0_REG,   0x00000081);    // LPC_EMC->StaticConfig0   = 0x00000081;
        _WDWORD(EMC_STA_WWEN0_REG,  0x00000003);    // LPC_EMC->StaticWaitWen0  = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
        _WDWORD(EMC_STA_WOEN0_REG,  0x00000003);    // LPC_EMC->StaticWaitOen0  = 0x00000003; /* ( n     ) -> 0 clock cycles */
        _WDWORD(EMC_STA_WRD0_REG,   0x00000006);    // LPC_EMC->StaticWaitRd0   = 0x00000006; /* ( n + 1 ) -> 7 clock cycles */
        _WDWORD(EMC_STA_WPAGE0_REG, 0x00000003);    // LPC_EMC->StaticWaitPage0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
        _WDWORD(EMC_STA_WWR0_REG,   0x00000005);    // LPC_EMC->StaticWaitWr0   = 0x00000005; /* ( n + 2 ) -> 7 clock cycles */
        _WDWORD(EMC_STA_WTURN0_REG, 0x00000003);    // LPC_EMC->StaticWaitTurn0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
    }
    
    
    init_emc();
    Setup();
    

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