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Problem with RL-TCPnet and SPI bus interrupt

hello forum
im using uvision V4.6.0.0 with MDK-ARM professional Version:4.60.0.0
toolchain.
i want to test RL-TCPnet with LPC1768 micro and DP83848C PHY Transiver
(i have designed a board myself as the same as your MCB17xx board).
i have loaded your LEDSwitch Example into my micro and it works fine
and i can send and recive data through UDP socket and i can control LED in my board.
i want to know in this example Ethernet controller works in Polling mode or interrupt mode???
my problem is that im using SPI bus in slave mode with interrupt service routin that i recive some datas from other controller(DSP)continuously and it works too but every time that i recive other packet through LAN my SPI peripheral hangs and dont recive other datas.
could you let me know how can i solve this problem?
im waiting for your answer.
best regards.
thanks.

Parents
  • Yes - it is a known problem with traditional SPI that the slave have only a half clock period to react and supply next data to send. One phase of the clock latches in one word to the slave, and next phase of clock the master picks up the first bit of the new word the slave wanted to send.

    So if running 100kHz clock frequency, then each clock period is 10us and a symmetrical clock would give 5us for receive interrupt to be serviced to pick up the incomming word and write the new word.

    So any interrupt routines or even polled code with critical sections can be enough to fail a transfer. Are you sure that the DSP requires you to make a decision what to send within that half clock cycle and can't use the more advanced transfer modes available?

Reply
  • Yes - it is a known problem with traditional SPI that the slave have only a half clock period to react and supply next data to send. One phase of the clock latches in one word to the slave, and next phase of clock the master picks up the first bit of the new word the slave wanted to send.

    So if running 100kHz clock frequency, then each clock period is 10us and a symmetrical clock would give 5us for receive interrupt to be serviced to pick up the incomming word and write the new word.

    So any interrupt routines or even polled code with critical sections can be enough to fail a transfer. Are you sure that the DSP requires you to make a decision what to send within that half clock cycle and can't use the more advanced transfer modes available?

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