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Gents;
Not a direct Keil question. I have picked up a project that has 2 serial FRAM (FM25V20-GTR) in the design.
I have read the specs and data sheets. The specman-ship make them sound the greatest thing since the pentode valve.
I would like to know what real world experiences might point to gotchas that I need watch for in terms both of software and hardware.
The design has good reverse termination on the serial lines and the devices have good by-pass decoupling. So I am assuming good SPI program design should make the FRAM devices quite happy.
Yes, I will be using Keil tools in the project.
Any and all comments are welcomed.
Thank you,
Bradford
I have had a datasheet on my desk for a few months for the 5v versions.
It looks to be directly compatible with standard E2 for reads and writes provided you use the correct number of address bytes. They don't seem to support bulk erase commands.
Writes can probably be sped up by changing your page size loop mask to the "full address range" and eliminating status register polling and / or associated delays.
The E2 chips I am using take 2-5 mS to write after the CS goes high from what I remember.
I should get my hands on one of these ... it is on the todo list.
Chad
Hi Chad;
Thanks for the feedback. This device (FM25V20-GTR) is a 3.3V device. It has life of 10E14 read/write cycles. I don't think I'll test that very much :-).
Unlike Serial Flash, the FM25V20 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been transferred to the device.
A quote from the specs. Yes, after a status check, CS must go back high prior to the next cycle but otherwise there is no delay other than the serial write time at 40MHz. There is no other write delay. There are no erase commands. Also, the device supports only Mode 0 and Mode 3 SPI protocols.
I understand your address concerns. The full 18 bit address selects an individual byte.
All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. This op-code is followed by a three-byte address value, which specifies the 18-bit address of the first data byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks.
Again from the spec sheet. Read works the same way except one dummy byte to prime the pump so to speak. I believe most serial memories support the same feature. 'Fast Read' is supported.
I will need to spend a bit more time with the data sheet before I write the world's greatest FRAM control functions.