STM32F4 FSMC set-up

In the following code the FSMC sets up the registers BCR and BTR (taken from the STM32F400 dev board code from Keil).

//  FSMC_Bank1->BTCR[(3-1)*2 + 1] =       /* Bank3 NOR/SRAM timing register configuration */
//                          (0 << 28) |   /* FSMC AccessMode A */
//                          (0 << 24) |   /* Data Latency */
//                          (0 << 20) |   /* CLK Division */
//                          (0 << 16) |   /* Bus Turnaround Duration */
//                          (9 <<  8) |   /* Data SetUp Time */
//                          (0 <<  4) |   /* Address Hold Time */
//                          (1 <<  0);    /* Address SetUp Time */

  FSMC_Bank1->BTCR[(3-1)*2 + 0] =       /* Bank3 NOR/SRAM timing register configuration */
                          (0 << 19) |   /* Write burst disabled */
                          (0 << 15) |   /* Async wait disabled */
                          (0 << 14) |   /* Extended mode disabled */
                          (0 << 13) |   /* NWAIT signal is disabled */
                          (1 << 12) |   /* Write operation enabled */
                          (0 << 11) |   /* NWAIT signal is active one data cycle before wait state */
                          (0 << 10) |   /* Wrapped burst mode disabled */
                          (0 <<  9) |   /* Wait signal polarity active low */
                          (0 <<  8) |   /* Burst access mode disabled */
                          (1 <<  4) |   /* Memory data  bus width is 16 bits */
                          (0 <<  2) |   /* Memory type is SRAM */
                          (0 <<  1) |   /* Address/Data Multiplexing disable */
                          (1 <<  0);    /* Memory Bank enable */

but the registers are in address order BCR1, BCR2, BCR3, BCR4, BTR1, BTR2, BTR3, BTR4
Therefore why is Bank 3 not FSMC_Bank1->BTCR[2] for BCR3 or FSMC_Bank1->BTCR[6] for BTR3

This works but it confused me as I was trying all morning with my custom board with the following

        FSMC_Bank1->BTCR[2] = FSMC_BCR1_WREN   |    /* Bank Write enable            */
                              FSMC_BCR1_MWID_0 |    /* Memory databus width 16bit   */
                              FSMC_BCR1_MBKEN  ;    /* Memory bank enable bit       */

Konrad