Hello Cortex M3 experts,
I have a FreeRTOS task that runs in Thread/unprivileged mode. When that task tries to execute a SVC instruction, I get a hard fault. But if the task is launched in privileged mode, that does not happen. The strange thing is that it happens in this code:
__asm portBASE_TYPE portRaisePrivilege( void ) { mrs r0, control tst r0, #1 ; Is the task running privileged? */ itte ne movne r0, #0 ; CONTROL[0]!=0, return false. */ svcne #portSVC_RAISE_PRIVILEGE ; Switch to privileged. */ moveq r0, #1 ; CONTROL[0]==0, return true. */ bx lr }
which is invoked by these calls:
void vPortExitCritical( void ) { portBASE_TYPE xRunningPrivileged = portRaisePrivilege() ; uxCriticalNesting--; if( uxCriticalNesting == 0 ) { portENABLE_INTERRUPTS(); } portRESET_PRIVILEGE( xRunningPrivileged ) ; }
and
void vPortEnterCritical( void ) { portBASE_TYPE xRunningPrivileged = portRaisePrivilege() ; portDISABLE_INTERRUPTS(); uxCriticalNesting++; portRESET_PRIVILEGE( xRunningPrivileged ) ; }
If I call the functions like this:
vPortEnterCritical() ; vPortExitCritical() ;
the hard fault will occur during the call to "vPortExitCritical". Any ideas?
I have noticed that if interrupts are disabled, the failure will occur. I changed BASEPRI to 0x0 and it did not cause the failure. But the priority of my SVC interrupt is 31. So in order for this to work, must I increase the NVIC priority of SVC (to 4)?
I mentioned SVC interrupt priority 4 because disabling interrupts in the sample above sets BASEPRI to 0x28.
If you disable interrupts and call an SVC a hard fault will occur. ARM7 uses SWI (interrupts diabled) whereas Cortex uses SVC (interrupts enabled). HAd a note in my code about it.
FYI (pg 3):
www.redacom.ch/.../rtx_article.pdf
You have said, you moved away from Keil. Don't you think you should post your mesasge here:
http://www.freertos.org/
No, because I compile the code using the ARM compiler. It is a border line case, I guess.
No, because I compile the code using the ARM compiler.
I use a spanner from Farnell on my car.
You think I speak to Farnell about the oil pump?
I believe this forum is a appropriate for such a question. In fact. FreeRTOS's discussion forum is much less appropriate as this is a question concerning the Cortex M3 core itself. This issue could have risen in any program exhibiting similar ISR priority schemes.
I believe this forum is a appropriate for such a question.
FWIW so do I. I was just being my normal facetious self ;)